TAS5815PWPR datasheet(44/123 Pages) TI

44 / 123 page

Table 7-4. I2 C Target Address Configuration (continued)

ADR/ FAULT PIN

Configuration

MSBs

User Define

LSB

120kΩ to DVDD

R/ W

7.5.2.1 Random Write

As shown in Figure 7-10, a single-byte data-write transfer begins with the master device transmitting a start

condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of

the data transfer. For a write data transfer, the read/write bit is a 0. After receiving the correct I2C device address

and the read/write bit, the device responds with an acknowledge bit. Next, the master transmits the address

byte corresponding to the internal memory address being accessed. After receiving the address byte, the device

again responds with an acknowledge bit. Next, the master device transmits the data byte to be written to the

memory address being accessed. After receiving the data byte, the device again responds with an acknowledge

bit. Finally, the master device transmits a stop condition to complete the single-byte data-write transfer.

Acknowledge

Start

Condition

2C Device Address

and R/W Bit

Subaddress

Data Byte

Stop

Condition

ACK

A0 ACK

A0 R/W ACK A7

Figure 7-10. Random Write Transfer

7.5.2.2 Random Read

As shown in Figure 7-11, a single-byte data-read transfer begins with the master device transmitting a start

condition followed by the I2C device address and the read/write bit. For the data-read transfer, both a write

followed by a read are actually done. Initially, a write is done to transfer the address byte of the internal memory

address to be read. As a result, the read/write bit is a 0. After receiving the address and the read/write bit,

the device responds with an acknowledge bit. In addition, after sending the internal memory address byte, the

master device transmits another start condition followed by the address and the read/write bit again. This time

the read/write bit is a 1, indicating a read transfer. After receiving the address and the read/write bit, the device

again responds with an acknowledge bit. Next, the device transmits the data byte from the memory address

being read. After receiving the data byte, the master device transmits a not-acknowledge followed by a stop

condition to complete the single-byte data-read transfer.

Not

Acknowledge

Start

Condition

2C Device Address

and R/W Bit

Subaddress

2C Device Address

and R/W Bit

Data Byte

Stop

Condition

ACK

A0 R/W

ACK

Repeat Start

Condition

ACK

Figure 7-11. Random Read Transfer

7.5.2.3 Sequential Write

A sequential data-write transfer is identical to a single-byte data-write transfer except that multiple data bytes

are transmitted by the master to the device as shown in Figure 7-12. After receiving each data byte, the device

responds with an acknowledge bit and the I2 subaddress is automatically incremented by one.

TAS5815

SLOSEA8 – DECEMBER 2024

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