SC16C852LIB datasheet(41/60 Pages) PHILIPS

41 / 60 page

SC16C852L_2

Product data sheet

Rev. 02 — 25 January 2007

41 of 60

NXP Semiconductors

SC16C852L

1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder

10. Dynamic characteristics

[1]

Applies to external clock, crystal oscillator max 24 MHz.

[2]

Maximum frequency =

[3]

10 % of the data bus output voltage level.

[4]

RCLK is an internal signal derived from Divisor Latch LSB (DLL) and Divisor Latch MSB (DLM) divisor latches.

Table 39.

Dynamic characteristics - Intel or 16 mode

Tamb = −40 °C to +85 °C; VDD = 1.65 V to 1.95 V; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

tWH

pulse width HIGH

tWL

pulse width LOW

tw(clk)

clock pulse width

12.5

fXTAL1

frequency on pin XTAL1

[1][2] --80

MHz

tsu(A)

address setup time

th(A)

address hold time

td(CS-IOR)

delay time from CS to IOR

td(IOW-TXRDYH) delay time from IOW to TXRDY HIGH

td(IOR-RXRDYH) delay time from IOR to RXRDY HIGH

td(stop-RXRDY)

delay time from stop to RXRDY

[4] --1TRCLK

td(start-TXRDY)

delay time from start to TXRDY

[4] --8TRCLK

tw(IOR)

IOR pulse width time

th(IOR-CS)

hold time from IOR to chip select

td(IOR)

IOR delay time

td(IOR-Q)

delay time from IOR to data output

25 pF load

tdis(IOR-QZ)

disable time from IOR to high-impedance

data output[3]

25 pF load

td(CSL-IOWL)

delay time from CS LOW to IOW LOW

--ns

tw(IOW)

IOW pulse width time

th(IOW-CS)

hold time from IOW to CS

--ns

td(IOW)

IOW delay time

tsu(D-IOWH)

setup time from data input to IOW HIGH

th(IOWH-D)

data input hold time after IOW HIGH

td(IOW-Q)

delay time from IOW to data output

25 pF load

td(modem-INT)

delay time from modem to INT

25 pF load

td(IOR-INTL)

delay time from IOR to INT LOW

25 pF load

td(stop-INT)

delay time from stop to INT

25 pF load

[4] --1TRCLK

td(start-INT)

delay time from start to INT

25 pF load

1TRCLK

td(IOW-TX)

delay time from IOW to TX

25 pF load

[4] 8TRCLK

24TRCLK

td(IOW-INTL)

delay time from IOW to INT LOW

25 pF load

tw(RESET)

pulse width on pin RESET

baud rate divisor

(216

− 1)

wclk

()

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