SC16C852LIB datasheet(34/60 Pages) PHILIPS

34 / 60 page

SC16C852L_2

Product data sheet

Rev. 02 — 25 January 2007

34 of 60

NXP Semiconductors

SC16C852L

1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder

7.14 Enhanced Feature Register (EFR)

Enhanced features are enabled or disabled using this register.

Bits 0 through 4 provide single or dual character software ﬂow control selection. When the

Xon1 and Xon2 and/or Xoff1 and Xoff2 modes are selected, the double 8-bit words are

concatenated into two sequential numbers.

[1]

Enhanced function control bits IER[7:4], ISR[5:4], FCR[5:4] and MCR[7:5].

Table 25.

Enhanced Feature Register bits description

Bit

Symbol

Description

EFR[7]

Automatic CTS ﬂow control.

logic 0 = automatic CTS ﬂow control is disabled (normal default condition)

logic 1 = enable automatic CTS ﬂow control. Transmission will stop when

CTS goes to a logical 1. Transmission will resume when the CTSA/CTSB pin

returns to a logical 0.

EFR[6]

Automatic RTS ﬂow control. Automatic RTS may be used for hardware ﬂow

control by enabling EFR[6]. When Auto-RTS is selected, an interrupt will be

generated when the receive FIFO is ﬁlled to the programmed trigger level and

RTS will go to a logic 1 at the next trigger level. RTS will return to a logic 0 when

data is unloaded below the next lower trigger level (programmed trigger level 1).

The state of this register bit changes with the status of the hardware ﬂow

control. RTS functions normally when hardware ﬂow control is disabled.

logic 0 = automatic RTS ﬂow control is disabled (normal default condition)

logic 1 = enable automatic RTS ﬂow control

EFR[5]

Special Character Detect.

logic 0 = special character detect disabled (normal default condition)

logic 1 = special character detect enabled. The SC16C852L compares each

incoming receive character with Xoff2 data. If a match exists, the received

data will be transferred to FIFO and ISR[4] will be set to indicate detection of

special character. Bit-0 in the X-registers corresponds with the LSB bit for the

receive character. When this feature is enabled, the normal software ﬂow

control must be disabled (EFR[3:0] must be set to a logic 0).

EFR[4]

Enhanced function control bit. The content of IER[7:4], ISR[5:4], FCR[5:4], and

MCR[7:5] can be modiﬁed and latched. After modifying any bits in the enhanced

registers, EFR[4] can be set to a logic 0 to latch the new values. This feature

prevents existing software from altering or overwriting the SC16C852L

enhanced functions.

logic 0 = disable/latch enhanced features[1]. (Normal default condition.)

logic 1 = enables the enhanced functions[1].

3:0

EFR[3:0]

Cont-3:0 TX, RX control. Logic 0 or cleared is the default condition.

Combinations of software ﬂow control can be selected by programming these

bits. See Table 26.

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