SC16C852LIB datasheet(38/60 Pages) PHILIPS

38 / 60 page

SC16C852L_2

Product data sheet

Rev. 02 — 25 January 2007

38 of 60

NXP Semiconductors

SC16C852L

1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder

7.22 Advanced Feature Control Register 1 (AFCR1)

[1]

It takes 4 XTAL1 clocks to reset the device.

Table 34.

Advanced Feature Control Register 1 register bits description

Bit

Symbol

Description

AFCR1[7]

Concurrent write. When this bit is set the host can write concurrently to

the same register of all channel.

logic

logic 0 = Normal operation

logic 1 = Concurrent Write operation

6:5

AFCR1[6:5]

reserved

AFCR1[4]

Sleep RXLow. Program RX input to be edge-sensitive or level-sensitive.

logic 0 = RX input is level-sensitive. If RXA/RXB pin is LOW, the UART

will not go to sleep. Once the UART is in Sleep mode, it will wake up if

RXA/RXB pin goes LOW.

logic 1 = RX input is edge-sensitive. UART will go to sleep even if

RXA/RXB pin is LOW, and will wake up when RXA/RXB pin toggles.

AFCR1[3]

reserved

AFCR1[2]

RTS/CTS mapped to DTR/DSR. Switch the function of RTS/CTS to

DTR/DSR.

logic 0 = RTS and CTS signals are used for hardware ﬂow control.

logic 1 = DTR and DSR signals are used for hardware ﬂow control.

RTS and CTS retain their functionality.

AFCR1[1]

SReset. Software Reset

A write to this bit will reset the UART. Once the UART is reset this bit is

automatically set to 0.[1]

AFCR1[0]

TSR Interrupt. Select TSR interrupt mode

logic 0 = transmit empty interrupt occurs when transmit FIFO falls

below the trigger level or becomes empty.

logic 1 = transmit empty interrupt occurs when transmit FIFO falls

below the trigger level, or becomes empty and the last stop bit has

been shifted out of the Transmit Shift Register.

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