PM7347 datasheet(19/341 Pages) PMC

19 / 341 page

S/UNI®-JET Data Sheet

Released

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use

Document ID: PMC-1990267, Issue 3

• Provides cell descrambling, header check sequence (HCS) error detection, idle cell filtering,

header descrambling (for use with PPP packets), and accumulates the number of received idle

cells, the number of received cells written to the FIFO, and the number of HCS errors.

• Provides a four cell FIFO for rate decoupling between the line, and a higher layer processing

entity. FIFO latency may be reduced by changing the number of operational cell FIFOs.

• Provides a receive HDLC controller with a 128-byte FIFO to accumulate data link

information.

• Provides detection of yellow alarm and loss of frame (LOF), and accumulates BIP-8 errors,

framing errors and FEBE events.

• Provides programmable pseudo-random test-sequence detection (up to 2

-1 bit length

patterns conforming to ITU-T O.151 standards) and analysis features.

The transmitter section of the S/UNI-JET:

• Provides frame insertion for the M23 or C-bit parity DS3 applications, alarm insertion, and

diagnostic features. Also:

° Optionally inserts far end alarm channel codes.

° Provides an integral HDLC transmitter is provided to insert the path maintenance data

link.

• Provides frame insertion for the G.751 or G.832 E3 applications, alarm insertion, and

diagnostic features. Also:

° Inserts the Trail Trace for G.832

° Provides an integral HDLC transmitter to insert either the Network Requirement or the

General Purpose data link.

• Provides frame insertion for G.704 6.312 Mbit/s J2 applications, alarm insertion, and

diagnostic features, and also an integral HDLC transmitter to insert the path maintenance data

link.

• Provides frame insertion and path overhead insertion for DS1, DS3, E1 or E3 based PLCP

formats, and also alarm insertion and diagnostic features.

• Provides a 50 MHz 8-bit wide or 16-bit wide Utopia FIFO buffer in the transmit path with

parity support and multi-PHY (Level 2) control signals.

• Provides optional ATM cell scrambling, header scrambling (for use with PPP packets), HCS

generation/insertion, programmable idle cell insertion, diagnostics features and accumulates

transmitted cells read from the FIFO.

• Provides a four cell FIFO for rate decoupling between the line and a higher layer processing

entity. FIFO latency may be reduced by changing the number of operational cells in the FIFO.

• Provides a transmit HDLC controller with a 128-byte FIFO.

• Provides an 8 kHz reference input for locking the transmit PLCP frame rate to an externally

applied frame reference.

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