PM7347 datasheet(45/341 Pages) PMC

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S/UNI®-JET Data Sheet

Released

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use

Document ID: PMC-1990267, Issue 3

Pin Name

Type

No.

Function

TADR[2]

TADR[1]

TADR[0]

Input

F18

F19

F20

The Transmit Address (TADR[2:0]) bus is used for

device selection and device polling in accordance with

the Utopia Level 2 standard.

When TADR[2:0] is set to the same value as the

PHY_ADR[2:0] inputs than the transmit interface of this

S/UNI-JET is either being selected or polled.

Note: The null-PHY address 7H is an invalid address and

cannot be used to select the S/UNI-JET.

TADR[2:0] is sampled on the rising edge of TFCLK.

TCA

Output

H19

The Transmit Multi-PHY Cell Available (TCA) signal

indicates when a cell is available in the transmit FIFO for

the device selected by TADR[2:0].

When high, TCA indicates that the corresponding

transmit FIFO is not full and a complete cell may be

written. When TCA goes low, it can be configured to

indicate either that the corresponding transmit FIFO is

near full or that the corresponding transmit FIFO is full.

TCA will transition low on the rising edge of TFCLK

which samples Payload byte 43 (TCALEVEL0=0) or 47

(TCALEVEL0=1) for the 8-bit interface (ATM8=1), or the

rising edge of TFCLK which samples Payload word 19

(TCALEVEL0=0) or 23 (TCALEVEL0=1) for the 16-bit

interface (ATM8=0) if the device being polled is the same

as the selected device.

To reduce FIFO latency, the FIFO depth at which TCA

indicates "full" can be set to one, two, three, or four cells.

Note: Regardless of what fill level TCA is set to indicate

"full" at, the transmit cell processor can store four

complete cells.

TCA is tri-stated when either the null-PHY address (7H)

or an address not matching the address space set by

PHY_ADR[2:0] is latched (by TFCLK) from the

TADR[2:0] inputs.

The polarity of TCA (with respect the the description

above) is inverted when the TCAINV register bit is set to

logic one.

TFCLK

Input

E20

The Transmit FIFO Write Clock (TFCLK) is used to write

ATM cells to the four-cell transmit FIFOs. TFCLK cycles

at a 52 MHz or lower instantaneous rate.

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