www.ti.com

EXAMPLE BOARD LAYOUT

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

(8.5)

(8.5)

44X (0.5)

48X (1.6)

48X (0.3)

(

0.2) TYP

VIA

(3.62)

(

6.5)

NOTE 10

(R0.05) TYP

(1.1 TYP)

(1.1 TYP)

(3.62)

PowerPAD

HTQFP - 1.2 mm max height

PHP0048E

4226616 /A 02/2021

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

8. This package is designed to be soldered to a thermal pad on the board. See technical brief, Powerpad thermally enhanced package,

Texas Instruments Literature No. SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).

9. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged

or tented.

10. Size of metal pad may vary due to creepage requirement.

TM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

SYMM

SYMM

48

37

13

24

25

36

1

12

SOLDER MASK

DEFINED PAD

METAL COVERED

BY SOLDER MASK

49

SEE DETAILS

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

EXPOSED METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

SOLDER MASK

DEFINED

EXPOSED METAL