7549 datasheet(25/73 Pages) RENESAS

25 / 73 page

Rev.2.00

Mar 05, 2007

Page 25 of 70

REJ03B0202-0200

7549 Group

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to change.

Fig 22. Structure of timer mode register

Fig 23. Structure of timer count source set register

Fig 24. Block diagram of timer 1 and timer 2

Timer mode register

(TM: address 002B16, initial value: 0016)

Not used (return “0” when read)

Timer 2 count stop bit

0: Count start

1: Count stop

P13/T2OUT output valid bit

0: Pulse output invalid (I/O port)

1: Pulse output valid

T2OUT polarity selection bit

0: Start from “H” level

1: Start from “L” level

Timer 2 write control bit

0: Write to latch and timer simultaneously

1: Write to only latch

Timer A write control bit

0: Write to latch and timer simultaneously

1: Write to only latch

Timer A count stop bit

0: Count start

1: Count stop

Not used (return “0” when read)

Timer count source set register

(TCSS: address 002C16, initial value: 0016)

Timer 2 count source selection bit

b1 b0

0 0 :

φSOURCE/16

0 1 :

φSOURCE/256

1 0 : Prescaler 12 output

1 1 : Timer A underflow signal

Timer A count source selection bit (Note 1)

b4 b3 b2

0 0 0 :

φSOURCE/16

0 0 1 :

φSOURCE/2

0 1 0 :

φSOURCE/32

0 1 1 :

φSOURCE/64

1 0 0 :

φSOURCE/128

1 0 1 :

φSOURCE/256

1 1 0 : Low-speed on-chip oscillator output

1 1 1 : XCIN input clock

(32kHz quartz crystal oscillation)

Prescaler 12 count source selection bit

0 :

φSOURCE/16

1 : XCIN input clock

(32kHz quartz crystal oscillation)

Not used (return “0” when read)

Note 1:

φSOURCE is the clock selected by bits 5 and 4 in the clock mode register (003716).

The timer count sources are not affected by bits 7 and 6, the CPU clock dividing

ratio select bits.

Data bus

Timer 1

interrupt

request

SOURCE/16

XCIN input clock

(32kHz quartz

crystal oscillation)

Data bus

Prescaler 12 latch (8)

Timer 1 latch (8)

Prescaler 12 (8)

Timer 1 (8)

φSOURCE/256

φSOURCE/16

Timer 2 count

stop bit

Timer 2 count

source selection bit

Prescaler 12 count

source selection bit

Timer 2

interrupt

request

Timer 2 latch (8)

Timer 2 (8)

Timer A underflow

Timer 2 write

control bit

Toggle flip-flop

P13/T2OUT output valid bit

T2OUT polarity

selection bit

“1”

“0”

P13/T2OUT

output valid bit

Port P13 latch

Port P13

direction

P13/T2OUT

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