7549 datasheet(9/73 Pages) RENESAS

9 / 73 page

Rev.2.00

Mar 05, 2007

Page 9 of 70

REJ03B0202-0200

7549 Group

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to change.

Fig 6.

Interrupt request

(Note)

M(S)

←(PCH)

(S)

←(S) − 1

M(S)

←(PCL)

(

←(S) − 1

Execute RTS

Subroutine

(S)

←(S) + 1

(PCL)

←M(S)

(S)

←(S) + 1

(PCH)

←M(S)

M(S)

←(PCH)

(S)

←(S) − 1

M(S)

←(PCL)

(S)

←(S) − 1

M(S)

←(PS)

(S)

←(S) − 1

Interrupt

Service Routine

(S)

←(S) + 1

(PS)

←M(S)

(S)

←(S) + 1

(PCL)

←M(S)

(S)

←(S) + 1

(PCH)

←M(S)

Execute JSR

Execute RTI

Store Return Address

on Stack

Store Contents of

Processor

Status Register on Stack

I Flag “0” to “1”

Fetch the Jump Vector

Restore Contents of

Processor Status Register

Restore Return

Address

Restore Return

Address

Store Return

Address

on Stack

Note : The condition to enable the interrupt

→ Interrupt enable bit is “1”

Interrupt disable flag is “0”

On-going Routine

Table 4

Push and pop instructions of accumulator or processor status register

Push instruction to stack

Pop instruction from stack

Accumulator

PHA

PLA

Processor status register

PHP

PLP

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