7549 datasheet(53/73 Pages) RENESAS

53 / 73 page

Rev.2.00

Mar 05, 2007

Page 53 of 70

REJ03B0202-0200

7549 Group

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to change.

NOTES ON PROGRAMMING

(1) Processor Status Register

The contents of the processor status register (PS) after reset are

undefined except for the interrupt disable flag I which is “1”.

After reset, initialize flags which affect program execution. In

particular, it is essential to initialize the T flag and the D flag

because of their effect on calculations.

(2) Interrupts

The contents of the interrupt request bit do not change even if the

BBC or BBS instruction is executed immediately after they are

changed by program because this instruction is executed for the

previous contents. For executing the instruction for the changed

contents, execute one instruction before executing the BBC or

BBS instruction.

(3) Decimal Calculations

• For calculations in decimal notation, set the decimal mode

flag D to “1”, then execute the ADC instruction or SBC

instruction. In this case, execute SEC instruction, CLC

instruction or CLD in-struction after executing one

instruction before the ADC instruction or SBC instruction.

• In the decimal mode, the values of the N (negative), V

(overflow) and Z (zero) flags are invalid.

(4) Ports

The values of the port direction registers cannot be read. That is,

it is impossible to use the LDA instruction, memory operation

instruction when the T flag is “1”, addressing mode using

direction register values as qualifiers, and bit test instructions

such as BBC and BBS.

It is also impossible to use bit operation instructions such as CLB

and SEB and read/modify/write instructions of direction registers

for calculations such as ROR.

For setting direction registers, use the LDM instruction, STA in-

struction, etc.

(5) A/D Conversion

Do not execute the STP instruction during A/D conversion.

(6) Instruction Execution Timing

The instruction execution time can be obtained by multiplying

the frequency of the internal clock

φ by the number of cycles

mentioned in the machine-language instruction table.

The frequency of the internal clock

φ is the same as that of the

φSOURCE in double-speed mode, twice the φSOURCE cycle in

high-speed mode, 4 times the

φSOURCE cycle in middle-speed

mode and 8 times the

φSOURCE cycle in low-speed mode.

(7) CPU Mode Register

The processor mode bits can be written only once after releasing

reset. Always set them to “002”. After written, rewriting any data

to these bits is disabled because they are locked. (Emulator MCU

is excluded.)

Also, the stack page bit (bit 2) is not locked.

In order to prevent error-writing to the processor mode bits (at

program runaway), write the CPU mode register at the start of

the program that runs after releasing reset.

(8) State transition

Do not stop the clock selected as the operation clock because of

setting of bits 0 to 2.

NOTES ON HARDWARE

(1) Handling of Power Source Pin

In order to avoid a latch-up occurrence, connect a capacitor

suitable for high frequencies as bypass capacitor between power

source pin (VCC pin) and GND pin (VSS pin). A ceramic

capacitor of 0.01

µF to 0.1 µF is recommended.

Connect a capacitor across the power source pin and GND pin

with the shortest possible wiring.

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