7549 datasheet(37/73 Pages) RENESAS

37 / 73 page

Rev.2.00

Mar 05, 2007

Page 37 of 70

REJ03B0202-0200

7549 Group

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to change.

A/D Converter

The functional blocks of the A/D converter are described below.

[AD conversion register] AD

The A/D conversion register is a read-only register that stores the

result of A/D conversion. Do not read out this register during an

A/D conversion.

[AD control register] ADCON

The AD control register controls the A/D converter.

Bit 2 to 0 are analog input pin selection bits.

Bit 3 is the AD conversion clock selection bit. When “0” is set to

this bit, the A/D conversion clock is

φSOURCE/2 and the A/D

conversion time is 122 cycles of

φSOURCE. When “1” is set to

this bit, the A/D conversion clock is

φSOURCE and the A/D

conversion time is 61 cycles of

φSOURCE.

Bit 4 is the AD conversion completion bit. The value of this bit

remains at “0” during A/D conversion, and changes to “1” at

completion of A/D conversion.

A/D conversion is started by setting this bit to “0”.

[Comparison voltage generator]

The comparison voltage generator divides the voltage between

VSS and VCC by 1024, and outputs the divided voltages.

[Channel selector]

The channel selector selects one of ports P17/AN7 to P10/AN0,

and inputs the voltage to the comparator.

[Comparator and control circuit]

The comparator and control circuit compares an analog input

voltage with the comparison voltage and stores its result into the

AD conversion register. When A/D conversion is completed, the

control circuit sets the AD conversion completion bit and the A/

D interrupt request bit to “1”. Because the comparator is

constructed linked to a capacitor, set

φSOURCE in order that the

A/D conversion clock is 250 kHz or over during A/D conversion.

• Notes on A/D converter

As for AD translation accuracy, on the following operating

conditions,

accuracy may become low.

(1) When VCC voltage is lower than [ 3.0 V ], the accuracy at

the low temperature may become extremely low compared

with that at room temperature. When the system would be

used at low temperature, the use at VCC = 3.0 V or more is

recommended.

(2) When XCIN or the low-speed on-chip oscillator is selected as

φSOURCE, the A/D converter cannot be used.

Fig 47. Structure of AD control register

Fig 48. Structure of AD conversion register

AD control register

(ADCON: address 003416, initial value: 1016)

Analog input pin selection bits

000: P10/AN0

001: P11/AN1

010: P12/AN2

011: P13/AN3

100: P14/AN4

101: P15/AN5

110: P16/AN6

111: P17/AN7

AD conversion clock selection bit

φSOURCE/2

φSOURCE

AD conversion completion bit

0: Conversion in progress

1: Conversion completed

Not used (returns “0” when read)

Read 8-bit (Read only address 003516)

(Address 003516)

Read 10-bit (read in order address 003616, 003516)

(Address 003616)

(Address 003516)

Note: High-order 6-bit of address 003616 returns “0” when read.

b9 b8

b6 b5 b4 b3 b2 b1 b0

b8 b7 b6 b5 b4 b3 b2

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