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7549 bảng dữ liệu(PDF) 42 Page - Renesas Technology Corp |
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7549 bảng dữ liệu(HTML) 42 Page - Renesas Technology Corp |
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42 / 73 page ![]() Rev.2.00 Mar 05, 2007 Page 42 of 70 REJ03B0202-0200 7549 Group PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. Fig 56. Timing diagram at reset Notes 1: X : Undefined 2: The content of other registers is undefined when the microcomputer is reset. The initial values must be surely set before you use it. 3: Do not access to the SFR area including nothing. 4: When the setting by the function set ROM data 2 (FSROM2) is performed, the initial values of this bit at reset are changed. 001016 001116 001216 001316 001416 001516 Port P0 pull-up control register (PULL0) Port P1 pull-up control register (PULL1) 001916 Serial I/O status register (SIOSTS) 001A16 Serial I/O control register (SIOCON) 001B16 UART control register (UARTCON) 003016 003116 003216 003416 AD control register (ADCON) 003716 003816 Oscillation stop detection register (CLKSTP) 003916 Watchdog timer control register (WDTCON) 003A16 Interrupt edge selection register (INTEDGE) 003B16 CPU mode register (CPUM) 003C16 Interrupt request register 1 (IREQ1) 003D16 Interrupt request register 2 (IREQ2) 003E16 Interrupt control register 1 (ICON1) 003F16 Interrupt control register 2 (ICON2) Clock mode register (CLKM) Port P0 drive capacity control register (DCCR) 000116 Port P0 direction register (P0D) 000316 000516 000716 000C16 000D16 000E16 000F16 Timer A (low-order) (TAL) Timer A (high-order) (TAH) 002816 Prescaler 12 (PRE12) 002916 Timer 1 (T1) 002A16 002B16 002C16 002D16 002E16 Timer count source set register (TCSS) 002F16 Port P1 direction register (P1D) Port P2 direction register (P2D) Port P3 direction register (P3D) Capture/Compare register (low-order) (CRAL) Key-on wakeup input selection register (KEYS) Capture/Compare register (high-order) (CRAH) Capture/Compare register R/W pointer (CCRP) Compare output mode register (CMOM) Compare register re-load register (CMPR) Capture/Compare port register (CCPR) Capture/Compare status register (CCSR) Capture software trigger register (CSTR) Compare interrupt source set register (CISR) Capture mode register (CAPM) Timer mode register (TM) Timer 2 (T2) (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) (21) (22) (23) (24) (25) (26) (27) (28) (29) (30) (31) (32) (33) (34) (35) (36) (37) (38) 0016 0016 0016 0016 0016 0016 0016 0016 1 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 Note4 0 0016 0016 FF16 FF16 FF16 FF16 1 1 1 1 1 1 0 0 0 0 0 0 0 1 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 |
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