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4571 bảng dữ liệu(PDF) 7 Page - Renesas Technology Corp |
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4571 bảng dữ liệu(HTML) 7 Page - Renesas Technology Corp |
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7 / 126 page ![]() Rev.1.02 May 25, 2007 Page 7 of 124 REJ03B0179-0102 4571 Group CONNECTIONS OF UNUSED PINS Note 1.If a port input instruction (SZD, IAP0, IAP1, IAP2, IAP3) is executed when the output latch is 1, the supply voltage may be increased in the instruction execution cycle by the through current. Note 2.Do not select the CNTR0 input as the timer 1 count source. (W11 W10 ≠11) Note 3.Set the input of INT0 pin or INT1 pin to be disabled. (I13=0, I23=0) Note 4.Set the output of the CNTR1 pin to be invalid. (W33=0) (Note when connecting to VSS or VDD) Connect the unused pins to VSS using the thickest wire at the shortest distance against noise. Table 7 Port function Pin Connection Usage condition Output structure Pull-up transistor Key-on wakeup Value of output latch Others D0 −D3 P30, P31 Open. N-channel open-drain −− 0/1 (Note 1) CMOS −− 0/1 − Connect to VSS. N-channel open-drain −− 0/1 − CMOS −− 0 − Connect to VDD. N-channel open-drain −− 1 − CMOS −− 1 − D4/CNTR0 Open. N-channel open-drain −− 0/1 (Notes 1, 2) Connect to VSS. N-channel open-drain −− 0/1 (Note 2) Connect to VDD. N-channel open-drain −− 1 (Note 2) P00 −P03, P10 −P13 Open. N-channel open-drain OFF Invalid 0/1 (Note 1) ON Invalid 1 − Connect to VSS. N-channel open-drain OFF Invalid 0/1 − Connect to VDD. N-channel open-drain ON/OFF Valid/Invalid 1 − P20/INT0 P21/INT1 Open. N-channel open-drain OFF Invalid 0/1 (Notes 1, 3) ON Invalid 1 (Note 3) Connect to VSS. N-channel open-drain OFF Invalid 0/1 (Note 3) Connect to VDD. N-channel open-drain ON/OFF Valid/Invalid 1 (Note 3) C/CNTR1 Open. CMOS −− 0/1 − Connect to VSS.CMOS −− 0 (Note 4) K Connect to VSS. −− Invalid −− Connect to VDD. −− Valid/Invalid −− |
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