ST7LITE49M datasheet(48/188 Pages) STMICROELECTRONICS

48 / 188 page

Supply, reset and clock management

ST7LITE49M

48/188

Bit 3 = Reserved, must be kept cleared

Bit 2 = LVDRF LVD reset flag

This bit indicates that the last Reset was generated by the LVD block. It is set by

hardware (LVD reset) and cleared by software (by reading). When the LVD is disabled

by option byte, the LVDRF bit value is undefined.

The LVDRF flag is not cleared when another RESET type occurs (external or

watchdog), the LVDRF flag remains set to keep trace of the original failure.

In this case, a watchdog reset can be detected by software while an external reset can

not.

Bit 1 = AVDF Voltage Detector flag

This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an interrupt

request is generated when the AVDF bit is set. Refer to Figure 19 and to Section for

additional details.

0: VDD over AVD threshold

1: VDD under AVD threshold

Bit 0 = AVDIE Voltage Detector Interrupt Enable bit

This bit is set and cleared by software. It enables an interrupt to be generated when the

AVDF flag is set. The pending interrupt information is automatically cleared when

software enters the AVD interrupt routine.

0: AVD interrupt disabled

1: AVD interrupt enabled

Table 11.

Reset source selection

RESET source

LVDRF

WDGRF

External RESET pin

Watchdog

LVD

Table 12.

Clock register mapping and reset values

Address

(Hex.)

label

003Ah

MCCSR

Reset

Value

MCO

SMS

003Bh

RCCR

Reset

Value

CR9

CR8

CR7

CR6

CR5

CR4

CR3

CR2

003Ch

SICSR

Reset

Value

CR1

CR0

WDGRF

LVDRF

AVDF

AVDIE

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