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ST7LITE49M bảng dữ liệu(PDF) 89 Page - STMicroelectronics |
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ST7LITE49M bảng dữ liệu(HTML) 89 Page - STMicroelectronics |
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89 / 188 page  ST7LITE49M On-chip peripherals 89/188 Since the Input Capture flags (ICF) for both timers (AT4 timer and LT timer) are set when signal transition occurs, software must mask one interrupt by clearing the corresponding ICIE bit before setting the ICS bit. If the ICS bit changes (from 0 to 1 or from 1 to 0), a spurious transition might occur on the Input Capture signal because of different values on LTIC and ATIC. To avoid this situation, it is recommended to do as follows: 1. First, reset both ICIE bits. 2. Then set the ICS bit. 3. Reset both ICF bits. 4. And then set the ICIE bit of desired interrupt. Computing a pulse length in long Input Capture mode is not straightforward since both timers are used. The following steps are required: 1. At the first Input Capture on the rising edge of the pulse, we assume that values in the registers are the following: – LTICR = LT1 – ATICRH = ATH1 – ATICRL = ATL1 – Hence ATICR1 [11:0] = ATH1 & ATL1. Refer to Figure 48 on page 90. 2. At the second Input Capture on the falling edge of the pulse, we assume that the values in the registers are as follows: – LTICR = LT2 – ATICRH = ATH2 – ATICRL = ATL2 – Hence ATICR2 [11:0] = ATH2 & ATL2. Now pulse width P between first capture and second capture is given by: where N is the number of overflows of 12-bit CNTR1. P decimal F9 LT1 – LT2 1 ++ () × 0.004ms × decimal FFF N × () N ATICR2 ATICR1 – 1 – ++ () 1ms × + = |
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