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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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ST7LITE49M bảng dữ liệu(PDF) 27 Page - STMicroelectronics |
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ST7LITE49M bảng dữ liệu(HTML) 27 Page - STMicroelectronics |
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27 / 188 page  ST7LITE49M Data EEPROM 27/188 Figure 8. Data EEPROM write operation 1. If a programming cycle is interrupted (by a reset action), the integrity of the data in memory is not guaranteed. 5.4 Power saving modes 5.4.1 Wait mode The DATA EEPROM can enter Wait mode on execution of the WFI instruction of the microcontroller or when the microcontroller enters Active-Halt mode.The DATA EEPROM will immediately enter this mode if there is no programming in progress, otherwise the DATA EEPROM will finish the cycle and then enter Wait mode. 5.4.2 Active-Halt mode Refer to Wait mode. 5.4.3 Halt mode The DATA EEPROM immediately enters Halt mode if the microcontroller executes the HALT instruction. Therefore the EEPROM will stop the function in progress, and data may be corrupted. 5.5 Access error handling If a read access occurs while E2LAT=1, then the data bus will not be driven. If a write access occurs while E2LAT=0, then the data on the bus will not be latched. If a programming cycle is interrupted (by a RESET action), the integrity of the data in memory will not be guaranteed. Byte 1 Byte 2 Byte 32 PHASE 1 Programming cycle Read operation impossible PHASE 2 Read operation possible E2LAT bit E2PGM bit Writing data latches Waiting E2PGM and E2LAT to fall Set by USER application Cleared by hardware ⇓ Row / byte ⇒ 0 1 2 3 ... 30 31 Physical Address 0 00h...1Fh 1 20h...3Fh ... N Nx20h...Nx20h+1Fh ROW DEFINITION |
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