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ST7LITE49M bảng dữ liệu(PDF) 95 Page - STMicroelectronics

tên linh kiện ST7LITE49M
Giải thích chi tiết về linh kiện  8-bit MCU with single voltage Flash memory data EEPROM, ADC, 8/12-bit timers, and I²C interface
PDF  188 Pages
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
Trang chủ  http://www.st.com
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ST7LITE49M bảng dữ liệu(HTML) 95 Page - STMicroelectronics

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On-chip peripherals
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11.2.6
Register description
Timer Control Status register (ATCSR)
Reset value: 0x00 0000 (x0h)
Bit 7 = Reserved
Bit 6 = ICF Input Capture flag
This Bit is set by hardware and cleared by software by reading the ATICR register (a
read access to ATICRH or ATICRL clears this flag). Writing to this bit does not change
the bit value.
0: No Input Capture
1: An Input Capture Has Occurred
Bit 5 = ICIE IC Interrupt Enable bit
This bit is set and cleared by software.
0: Input Capture Interrupt Disabled
1: Input Capture Interrupt Enabled
Bits 4:3 = CK[1:0] Counter Clock Selection bits
These bits are set and cleared by software and cleared by hardware after a reset. they
select the clock frequency of the counter.
Bit 2 = OVF1 Overflow flag
This bit is set by hardware and cleared by software by reading the ATCSR register. It
indicates the transition of the Counter1 CNTR1 from FFFh to ATR1 value.
0: No Counter Overflow Occurred
1: Counter Overflow Occurred
Bit 1 = OVFIE1 Overflow Interrupt Enable bit
This bit is read/write by software and cleared by hardware after a reset.
0: Overflow Interrupt Disabled.
1: Overflow Interrupt Enabled.
7
0
0
ICF
ICIE
CK1
CK0
OVF1
OVFIE1
CMPIE
Read / Write
Table 36.
Counter clock selection
Counter clock selection
CK1
CK0
OFF
0
0
selection forbidden
1
1
fLTIMER (1 ms timebase @ 8 MHz)
0
1
fCPU
10



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