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CLRC663 bảng dữ liệu(PDF) 83 Page - NXP Semiconductors

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Giải thích chi tiết về linh kiện  High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus
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CLRC663 bảng dữ liệu(HTML) 83 Page - NXP Semiconductors

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NXP Semiconductors
CLRC663
High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus
Bit
7
6
5
4
3
2
1
0
Symbol
T4CounterValLo
Access
rights
dy
Table 129. T4CounterValLo register (address 27h)
Bit
Symbol
Description
7 to 0
T4CounterValLo
Low byte of the current counter value of the timer 4.
Table 130. T4CounterValLo bits
9.8 Transmitter driver configuration registers
9.8.1 DrvMode
Bit
7
6
5
4
3
2
1
0
Symbol
Tx2Inv
Tx1Inv
-
-
TxEn
TxClk Mode
Access
rights
r/w
r/w
RFU
RFU
r/w
r/w
Table 131. DrvMode register (address 28h)
Bit
Symbol
Description
7
Tx2Inv
Inverts transmitter 2 at TX2 pin
6
Tx1Inv
Inverts transmitter 1 at TX1 pin
5
RFU
4
-
RFU
3
TxEn
If set to 1 both transmitter pins are enabled
2 to 0
TxClkMode
Transmitter clock settings. Codes 011b and 0100b are not supported. This register
defines, if the output is operated in open-drain, push-pull, at high impedance or pulled to
a fix high or low level.
Table 132. DrvMode bits
9.8.2 TxAmp
With the set_cw_amplitude register, output power can be traded off against power supply rejection. Spending
more headroom leads to better power supply rejection ration and better accuracy of the modulation degree.
With CwMax set, the voltage of TX1 will be pulled to the maximum possible. This register overrides the settings
made by set_cw_amplitude.
Bit
7
6
5
4
3
2
1
0
Symbol
set_cw_amplitude
-
set_residual_carrier
Access
rights
r/w
RFU
r/w
Table 133. TxAmp register (address 29h)
CLRC663
All information provided in this document is subject to legal disclaimers.
© 2024 NXP B.V. All rights reserved.
Product data sheet
Rev. 5.3 — 3 January 2024
83 / 177



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