CLRC663 datasheet(75/177 Pages) NXP

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NXP Semiconductors

CLRC663

High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus

Bit

Symbol

Description

This value shall not be read out during reception.

Table 90. T0CounterValLo bits

9.7.2.5 T1Control

Control register of the Timer1.

Bit

Symbol

T1StopRx

T1Start

T1AutoRestart

T1Clk

Access

rights

r/w

RFU

r/w

RFU

r/w

Table 91. T1Control register (address 14h);

Bit

Symbol

Description

T1StopRx

If set, the timer stops after receiving the first 4 bits. If cleared, the timer is not stopped

automatically.

Note: If LFO trimming is selected by T1start, this bit has no effect.

RFU

5 to 4

T1Start

00b: The timer is not started automatically

01 b: The timer starts automatically at the end of the transmission

10 b: Timer is used for LFO trimming without underflow (Start/Stop on PosEdge)

11 b: Timer is used for LFO trimming with underflow (Start/Stop on PosEdge)

T1AutoRestart

Set to logic 1, the timer automatically restarts its countdown from T1ReloadValue, after

the counter value has reached the value zero.

Set to logic 0 the timer decrements to zero and stops.

The bit Timer1IRQ is set to logic 1 when the timer underflows.

RFU

1 to 0

T1Clk

00 b: The timer input clock is 13.56 MHz

01 b: The timer input clock is 211,875 kHz.

10 b: The timer input clock is an underflow of Timer0

11 b: The timer input clock is an underflow of Timer2

Table 92. T1Control bits

9.7.2.6 T1ReloadHi

High byte (MSB) reload value of the Timer1.

Bit

Symbol

T1ReloadHi

Access

rights

r/w

Table 93. T0ReloadHi register (address 15h)

CLRC663

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5.3 — 3 January 2024

75 / 177

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