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ADC3908CSSS bảng dữ liệu(PDF) 12 Page - Texas Instruments |
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ADC3908CSSS bảng dữ liệu(HTML) 12 Page - Texas Instruments |
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12 / 131 page ![]() 5.10 Timing Requirements Maximum and minimum values are specified over the operating free-air temperature range and nominal supply voltages. Typical values are specified at TA = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = IOVDD = 1.8 V, Internal 1.2 V reference, 5 pF output load, and –1-dBFS differential input, unless otherwise noted PARAMETER TEST CONDITIONS MIN NOM MAX UNIT ADC TIMING SPECIFICATIONS tAD Aperture Delay 0.5 ns tA Aperture Jitter square wave clock with fast edges 500 fs tACQ Signal acquisition period, referenced to sampling clock falling edge -TS/5 Sampling Clock Period tCONV Signal conversion period, referenced to sampling clock falling edge Fs = 25 MSPS 5.5 ns Fs = 65 MSPS 5.5 ns Fs = 125 MSPS 5.5 ns Wake up time Time to valid data after coming out of power down. Internal reference. 30 us Time to valid data after coming out of power down. External 1.2V reference. 19 us ADC Latency Signal input to data output Low Latency Mode (DDR) 1 ADC clock cycles Digital features enabled (SDR, Serial CMOS) 5 Add. Latency Real Decimation 2 25 4 60 8 130 16 270 INTERFACE TIMING - DDR CMOS tPD Propagation delay: sampling clock falling edge to DCLK rising edge TS/4 + 3ns ns tCD DCLK rising edge to output data delay Fs = 25 MSPS -11 -10 -9 Fs = 65 MSPS -4.8 -3.8 -2.8 Fs = 125 MSPS -3 -2 -1 tDV Data valid Fs = 25 MSPS 18 20 22 Fs = 65 MSPS 5.7 7.7 9.7 Fs = 125 MSPS 2 4 6 INTERFACE TIMING - SDR CMOS tPD Propagation delay: sampling clock falling edge to DCLK rising edge TS/4 + 3ns ns tCD DCLK rising edge to output data delay Fs = 25 MSPS -19 -20 -21 Fs = 65 MSPS -8.6 -7.6 -6.6 Fs = 125 MSPS -5 -4 -3 tDV Data valid Fs = 25 MSPS 38 40 42 Fs = 65 MSPS 13.4 15.4 17.4 Fs = 125 MSPS 6 8 10 ADC3910D125 SBASAD1 – DECEMBER 2023 www.ti.com 12 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: ADC3910D125 |
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