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ADC3908CSSS bảng dữ liệu(PDF) 59 Page - Texas Instruments

tên linh kiện ADC3908CSSS
Giải thích chi tiết về linh kiện  ADC3910Dx and ADC3910Sx 10-bit, 25 to 125-MSPS Low Latency, Low Power, Small, Single and Dual Channel ADC with Integrated Input Buffers
PDF  131 Pages
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Trang chủ  http://www.ti.com
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ADC3908CSSS bảng dữ liệu(HTML) 59 Page - Texas Instruments

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Table 6-21. PIN_CFG_1 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3:1
CLK_PIN_STRENGTH
R/W
0h
DCLK and DCLKZ output pin strength
000b = 15/15 (default)
001b = 13/15
010b = 11/15
011b = 9/15
100b = 7/15
101b = 5/15
110b = 3/15
111b = 1/15
0
RESERVED
R
0h
6.6.1.16 TEST_PAT_CFG Register (Address = 91h) [Reset = 0h]
Return to the Summary Table.
Table 6-22. TEST_PAT_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
3:0
DATA_PIN_STRENGTH
R/W
0h
D11 to D0 output pin strength
0000b = 15/15 (default)
0001b = 14/15
0010b = 13/15
0011b = 12/15
0100b = 11/15
0101b = 10/15
0110b = 9/15
0111b = 8/15
1000b = 7/15
1001b = 6/15
1010b = 5/15
1011b = 4/15
1100b = 3/15
1101b = 2/15
1110b = 1/15
1111b = 0/15 (Tri-state)
6.6.1.17 TEST_PATTERN_CFG Register (Address = 91h) [Reset = 00h]
Return to the Summary Table.
Table 6-23. TEST_PATTERN_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
6
TOGGLE_PAT
R/W
0h
Toggle mode for test pattern. Enable to toggle all lanes in SDR
mode, disable in DDR mode.
0b = Disable test pattern toggle
1b = Enable test pattern toggle
5
TEST_PAT_B
R/W
0h
Enables the test pattern in register 0x0092
0b = Channel B test pattern disabled
1b = Channel B test pattern enabled
4
TEST_PAT_A
R/W
0h
Enables the test pattern in register 0x0094
0b = Channel A test pattern disabled
1b = Channel A test pattern enabled
3:0
RESERVED
R
0h
6.6.1.18 TEST_PATTERN_CHB_7:0 Register (Address = 92h) [Reset = 00h]
Return to the Summary Table.
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ADC3910D125
SBASAD1 – DECEMBER 2023
Copyright © 2023 Texas Instruments Incorporated
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