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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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ADC3908CSSS bảng dữ liệu(PDF) 56 Page - Texas Instruments |
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ADC3908CSSS bảng dữ liệu(HTML) 56 Page - Texas Instruments |
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56 / 131 page  Table 6-13. DEV_CFG_1 Register Field Descriptions (continued) Bit Field Type Reset Description 3:0 RESERVED R 0h 6.6.1.8 DEV_CFG_2 Register (Address = 89h) [Reset = 00h] Return to the Summary Table. Table 6-14. DEV_CFG_2 Register Field Descriptions Bit Field Type Reset Description 7 DCLK_FL_DLY__0 R/W 0h Adjust the delay on the falling edge of DCLK where T is the period of DCLK. 0b = No adjustment 1b = T/20 (T/10 with HFSB = 1) 1010b = -T/10 (-T/5 with HFSB = 1) 1011b = -T/20 (-T/10 with HFSB = 1) 6 DIG_DCLK R/W 0h By default CLK is DCLK for digital blocks. Enable when CLK and DCLK are different and DCLKIN is used. 0b = CLK used as DCLK for digital blocks 1b = DCLKIN used as DCLK for digital blocks 5 DIG_DATA R/W 0h Data from digital block used as output data. 0b = Digital data to output data disabled 1b = Digital data to output data enabled 4:0 RESERVED R 0h 6.6.1.9 CLK_CFG_1 Register (Address = 8Ah) [Reset = 00h] Return to the Summary Table. Table 6-15. CLK_CFG_1 Register Field Descriptions Bit Field Type Reset Description 5 DIG_CLK_SEL R/W 0h By default CLK is DCLK for digital blocks. Enable when CLK and DCLK are different and DCLKIN is used. 0b = CLK used as CLK for digital blocks 1b = Relatched CLK using DCLKIN used as CLK for digital blocks 4 RESERVED R 0h 3 CHB_CLK R/W 0h Enable when only ADC channel A is disabled, ADC channel B is enabled and HDDR interface mode is used. 2:1 DCLK_RISE_DLY R/W 0h Adjust the delay on the rising edge of DCLK where T is the period of DCLK. 00b = No adjustment 01b = T/20 (T/10 with HFSB = 1) 10b = -T/10 (-T/5 with HFSB = 1) 11b = -T/20 (-T/10 with HFSB = 1) 0 DCLK_FL_DLY__1 R/W 0h Adjust the delay on the falling edge of DCLK where T is the period of DCLK. 0b = No adjustment 1b = T/20 (T/10 with HFSB = 1) 10b = -T/10 (-T/5 with HFSB = 1) 11b = -T/20 (-T/10 with HFSB = 1) 6.6.1.10 CLK_CFG_2 Register (Address = 8Bh) [Reset = 00h] Return to the Summary Table. ADC3910D125 SBASAD1 – DECEMBER 2023 www.ti.com 56 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: ADC3910D125 |
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