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ADC3908CSSS bảng dữ liệu(PDF) 52 Page - Texas Instruments

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Giải thích chi tiết về linh kiện  ADC3910Dx and ADC3910Sx 10-bit, 25 to 125-MSPS Low Latency, Low Power, Small, Single and Dual Channel ADC with Integrated Input Buffers
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ADC3908CSSS bảng dữ liệu(HTML) 52 Page - Texas Instruments

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6.6 Register Maps
Register Descriptions lists the SPI registers. All register offset addresses not listed in Register Descriptions
should be considered as reserved locations and the register contents should not be modified.
Table 6-6 shows the codes that are used for access types in this section.
6.6.1 Register Descriptions
Table 6-5. DEVICE Registers
Address
Register Name
0h
RESET
38h
CFG_ALERT
39h
SPARE_REG
84h
INTERLEAVE
85h
REF_EQ
88h
DEV_CFG_1
89h
DEV_CFG_2
8Ah
CLK_CFG_1
8Bh
CLK_CFG_2
8Ch
PDN_CFG
8Dh
DEV_CFG_3
8Eh
CLK_CFG_3
8Fh
CLK_CFG_4
90h
PIN_CFG_1
91h
TEST_PAT_CFG
91h
TEST_PATTERN_CFG
92h
TEST_PATTERN_CHB_7:0
93h
TEST_PATTERN_CHB_13:8
94h
TEST_PATTERN_CHA_7:0
95h
TEST_PATTERN_CHA_13:8
97h
GLOBAL_PDN
98h
INTERFACE_CFG_1
9Ch
INTERFACE_CFG_2
9Eh
HFSB_FPDN_CFG
A0h
INTERFACE_CFG_3
A1h
DIG_PATTERN_EN
A2h
DIG_PATTERN_CHA_7:0
A3h
DIG_PATTERN_CHA_15:8
A4h
DIG_PATTERN_CHB_7:0
A5h
DIG_PATTERN_CHB_15:8
A6h
INTERFACE_CFG_4
A7h
OUTPUT_DATA_WIDTH
A8h
DCLK_DIVIDER
AEh
OUTPUT_BIT_MAPPER_D0_D1
AFh
OUTPUT_BIT_MAPPER_D2_D3
B0h
OUTPUT_BIT_MAPPER_D4_D5
B1h
OUTPUT_BIT_MAPPER_D6_D7
B2h
OUTPUT_BIT_MAPPER_D8_D9
B3h
OUTPUT_BIT_MAPPER_D10_D11
ADC3910D125
SBASAD1 – DECEMBER 2023
www.ti.com
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