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ADC3908CSSS bảng dữ liệu(PDF) 37 Page - Texas Instruments

tên linh kiện ADC3908CSSS
Giải thích chi tiết về linh kiện  ADC3910Dx and ADC3910Sx 10-bit, 25 to 125-MSPS Low Latency, Low Power, Small, Single and Dual Channel ADC with Integrated Input Buffers
PDF  131 Pages
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ADC3908CSSS bảng dữ liệu(HTML) 37 Page - Texas Instruments

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Table 6-2. Decimation Filter Summary and Maximum Available Output Bandwidth
REAL DECIMATION
DECIMATION
SETTING (N)
OUTPUT RATE
OUTPUT
BANDWIDTH
OUTPUT RATE
(FS = 125 MSPS)
OUTPUT BANDWIDTH
(FS = 125 MSPS)
Real
2
FS / 2
0.8 × FS / (2 × 2)
62.5 MSPS
25 MHz
4
FS / 4
0.8 × FS / (4 × 2)
31.25 MSPS
12.5 MHz
8
FS / 8
0.8 × FS / (8 × 2)
15.625 MSPS
6.25 MHz
16
FS / 16
0.8 × FS / (16 × 2)
7.8125 MSPS
3.125 MHz
The decimation filter responses are normalized to the ADC sampling clock frequency FS and illustrated in Figure
6-12 to Figure 6-19. They are interpreted as follows:
Each figure contains the filter pass-band, transition band(s) and alias or stop-band(s) as shown in Figure 6-11.
The x-axis shows the offset frequency normalized to the ADC sampling rate FS.
For example, in the divide-by-4 setup, the output data rate is FS / 4 with a Nyquist zone of FS / 8 or 0.125 × FS.
The transition band (colored in blue) is centered around 0.125 × FS and the alias transition band is centered at
0.375 × FS. The stop-bands (colored in red), which alias on top of the pass-band, are centered at 0.25 × FS and
0.5 × FS.
Figure 6-11. Interpretation of the Decimation Filter Plots
Figure 6-12. Decimation by 2 frequency response
Figure 6-13. Decimation by 2 passband ripple
response
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ADC3910D125
SBASAD1 – DECEMBER 2023
Copyright © 2023 Texas Instruments Incorporated
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