USB97C100QFP datasheet(42/64 Pages) SMSC

42 / 64 page

SMSC DS – USB97C100

Page 42

Rev. 01/03/2001

Table 70 - Transmit FIFO Status Register A

TXSTAT_A

(0x7F60 - RESET=0x55)

TRANSMIT FIFO STATUS REGISTER A

BIT

NAME

R/W

DESCRIPTION

EP3TX_EMPTY

Endpoint 3 Transmit Packet FIFO Status

Bits [7:6]='11' Invalid

Bits [7:6]='10' Empty (No Packets queued)

Bits [7:6]='01' Full (5 Packets queued)

Bits [7:6]='00' Partially Full (1, 2, 3, or 4 Packets queued)

EP3TX_FULL

EP2TX_EMPTY

Endpoint 2 Transmit Packet FIFO Status

Bits [5:4]='11' Invalid

Bits [5:4]='10' Empty (No Packets queued)

Bits [5:4]='01' Full (5 Packets queued)

Bits [5:4]='00' Partially Full (1, 2, 3, or 4 Packets queued)

EP2TX_FULL

EP1TX_EMPTY

Endpoint 1 Transmit Packet FIFO Status

Bits [3:2]='11' Invalid

Bits [3:2]='10' Empty (No Packets queued)

Bits [3:2]='01' Full (5 Packets queued)

Bits [3:2]='00' Partially Full (1, 2, 3, or 4 Packets queued)

EP1TX_FULL

EP0TX_EMPTY

Endpoint 0 Transmit Packet FIFO Status

Bits [1:0]='11' Invalid

Bits [1:0]='10' Empty (No Packets queued)

Bits [1:0]='01' Full (5 Packets queued)

Bits [1:0]='00' Partially Full (1, 2, 3, or 4 Packets queued)

EP0TX_FULL

Table 71 - Transmit FIFO Status Register B

STAT_B

(0x7F61 - RESET=0x55)

TRANSMIT FIFO STATUS REGISTER B

BIT

NAME

R/W

DESCRIPTION

EP7TX_EMPTY

Endpoint 7 Transmit Packet FIFO Status

Bits [7:6]='11' Invalid

Bits [7:6]='10' Empty (No Packets queued)

Bits [7:6]='01' Full (5 Packets queued)

Bits [7:6]='00' Partially Full (1, 2, 3, or 4 Packets queued)

EP7TX_FULL

EP6TX_EMPTY

Endpoint 6 Transmit Packet FIFO Status

Bits [5:4]='11' Invalid

Bits [5:4]='10' Empty (No Packets queued)

Bits [5:4]='01' Full (5 Packets queued)

Bits [5:4]='00' Partially Full (1, 2, 3, or 4 Packets queued)

EP6TX_FULL

EP5TX_EMPTY

Endpoint 5 Transmit Packet FIFO Status

Bits [3:2]='11' Invalid

Bits [3:2]='10' Empty (No Packets queued)

Bits [3:2]='01' Full (5 Packets queued)

Bits [3:2]='00' Partially Full (1, 2, 3, or 4 Packets queued)

EP5TX_FULL

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