USB97C100QFP datasheet(22/64 Pages) SMSC

tên linh kiện	USB97C100QFP

Giải thích chi tiết về linh kiện	Multi-Endpoint USB Peripheral Controller

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nhà sản xuất	SMSC [SMSC Corporation]

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SMSC DS – USB97C100

Page 22

Rev. 01/03/2001

Table 26 - Utility Configuration Register

UTIL_CONFIG

(0x7F1B- RESET=0x00)

UTILITY CONFIGURATION REGISTER

BIT

NAME

R/W

DESCRIPTION

[7:4]

Reserved

GPIO3/T1

R/W

P3.5 Timer 1 input trigger source

0 = GPIO3

1 = SOF FRAME write strobe

GPIO2/T0

R/W

P3.4 Timer 0 input trigger source

0 = GPIO2

1 = SOF FRAME write strobe

GPIO1/TXD

R/W

GPIO1/TXD Output Select Mux

0 = GPIO1

1 = P3.1

GPIO0/RXD

R/W

P3.0 RXD/GPIO0 Input Select Mux

0 = RXD<=GPIO0

1 = RXD<='0'

Notes:

In Counter mode, the 8051 must sample T[1:0] as a '1' in one instruction cycle, and then '0' in the next. So for

12MHz, the SOF Pulse must be active for at least 1us.

Missing SOF packets can be reconstructed by using the Timer mode to count the number of 8051 instruction

cycles since the last valid Frame was received.

A GPIO can be used to output nSOF pulses. This can be done by configuring a GPIO as an output and writing

to the GPIO out register to generate low pulses each time a SOF packet is received.

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