USB97C100QFP datasheet(19/64 Pages) SMSC

19 / 64 page

SMSC DS – USB97C100

Page 19

Rev. 01/03/2001

Table 12 - Interrupt 1 Mask

IMR_1

(0x7F03- RESET=0xFF)

INTERRUPT 1 MASK REGISTER

BIT

NAME

R/W

DESCRIPTION

[7:5]

Reserved

EOT

R/W

EOT interrupt mask

0 = Enable Interrupt

1 = Mask Interrupt

SOF

R/W

Start of Frame Interrupt Mask

0 = Enable Interrupt

1 = Mask Interrupt

ALLOC

R/W

MCU Software Allocation Complete Interrupt Mask

0 = Enable Interrupt

1 = Mask Interrupt

RX_OVRN

R/W

Receive Overrun Interrupt Mask

0 = Enable Interrupt

1 = Mask Interrupt

PWR_MNG

R/W

Power Management Wakeup Interrupt Mask

0 = Enable Interrupt

1 = Mask Interrupt

Table 13 - Device Revision Register

DEV_REV

(0x7F06- RESET=0xXX)

DEVICE REVISION REGISTER

BIT

R/W

DESCRIPTION

[7:0]

Rev.

This register defines additional revision information

used internally by SMSC. The value is silicon revision

dependent.

Table 14 - Device Identification Register

DEV_ID

(0x7F07- RESET=0x25)

DEVICE IDENTIFICATION REGISTER

BIT

R/W

DESCRIPTION

[7:0]

BCD '25'

HEX 0x25

This register defines additional revision information

used internally by SMSC

Table 15– 8051 GP FIFO1

GP_FIFO1

(0x7F10- RESET=0xXX)

8051 GP FIFO1

BIT

NAME

R/W

DESCRIPTION

[7:0]

GP_FIFO1

R/W

8 byte deep GP FIFO. This data FIFOs must not be read

unless the associated status bit indicates that FIFO is not

empty.

Table 16– 8051 GP FIFO2

GP_FIFO2

(0x7F12 - RESET=0xXX)

8051 GP FIFO2

BIT

NAME

R/W

DESCRIPTION

[7:0]

GP_FIFO2

R/W

8 byte deep GP FIFO. This data FIFOs must not be read

unless the associated status bit indicates that FIFO is not

empty.

Table 17– 8051 GP FIFO3

GP_FIFO3

(0x7F14 - RESET=0xXX)

8051 GP FIFO3

BIT

NAME

R/W

DESCRIPTION

[7:0]

GP_FIFO3

R/W

8 byte deep GP FIFO. This data FIFOs must not be read

unless the associated status bit indicates that FIFO is not

empty.

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