TSS461C datasheet(37/57 Pages) ATMEL

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TSS461C

4193G–AUTO–12/04

Message Length And Status

The message length and status register at address (base_address + 0x03) is also 8 bits

wide. It indicates the length reserved for the message in the Message DATA RAM area.

•

Read/Write register.

M_L [4:0]: Message Length

The 5 high bits of this register allow the user to specify either the length of the message

to be transmitted, or the maximum length of a message receivable in the pointed recep-

tion buffer.

Note that the first byte in this register does not contain data, but the length of the mes-

sage received. This implies that the length value has to be equal to or greater than the

maximum length of a message to be received in this buffer (or the length of a message

to be transmitted) plus 1. Thus allowing a maximum length of 30 bytes and a minimum

length of 0 byte.

If the value of this field is illegal (i.e 0x00) then this message pointer is defined as being

a link (see section “Message Pointer Register” and Section “Linked Channels”).

CHER: Channel Error Status

and Abort Command

As status, this bit is set by the TSS461C when error occurs in transmission or on a

received frame. The user must reset it.

To abort the transmission defined in the channel, this bit can be set to1 by the user (see

Section “Retries, Rearbitrate and Abort” and Section “Abort”).

CHTx: Channel Transmitted and

Transmit Enable Command

54321

M_L 4

M_L 3

M_L 2

M_L 1

M_L 0

CHER

CHTx

CHRx

base_address

+ 0x03

M_L [4:0] = 0x00

Linked channel

M_L [4:0] = 0x01

Frame with no DATA field (*)

M_L [4:0] = 0x02

Frame with 1 DATA byte

- - - - - - -

- - - - - - - - - - - - - - - - - - - - - -

M_L [4:0] = 0x1D

Frame with 28 DATA bytes

M_L [4:0] = 0x1E

Frame with 29 DATA bytes

M_L [4:0] = 0x1F

Frame with 30 DATA bytes

(*) Different of a reply request frame with no in-frame reply (deferred reply).

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