TSS461C datasheet(26/57 Pages) ATMEL

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TSS461C

4193G–AUTO–12/04

The diagnosis is discussed in detail in Section “Diagnosis States”.

•

In its four high order bits the user can program the SDC rate SDC [3:0]

•

In its two medium order bits the diagnosis system mode is controlled: M1, M0

•

In the two low order bits, the user controls if the SDC and TIP are to be generated

automatically ETIP, ESDC

SDC [3:0]: SDC Divider

The input clock is the times lot clock.

Table 6. System Diagnosis Clock Divider

Ma, Mb: Operating Mode

Command Bits

Table 7. Diagnosis System Command Bits

ETIP: Enable Transmission In

Progress

One: Enable TIP generation

Zero: Disable TIP generation.

SDC Divider SDC [3:0]

Divide By

0000

0001

128

0010

256

0011

512

0100

1024

0101

2048

0110

4096

0111

8192

1000

16384

1001

32768

1010

65536

1011

131072

1100

262144

1101

524288

1110

1048576

1111

2097152

Forces the Communication on RxD0 (differential)

Forces the Communication on RxD2 (DATA)

Forces the Communication on RxD1 (DATA)

Automatic selection

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