AT80C51RB2-3CSIM datasheet(8/83 Pages) ATMEL

8 / 83 page

AT80C51RD2/AT83C51Rx2

4113B–8051–03/05

Oscillators

Overview

One oscillator is available for CPU:

•

OSC used for high frequency (3 MHz to 40 MHz)

In order to optimize the power consumption and the execution time needed for a specific

task, an internal prescaler feature has been implemented between the selected oscilla-

tor and the CPU.

Registers

Table 4. Clock Reload Register

Reset Value = 1111 1111b

Not bit addressable

Prescaler Divider

A hardware RESET puts the prescaler divider in the following state:

•

CKRL = FFh: F

CLK CPU = FCLK PERIPH = FOSC/2 (Standard C51 feature)

KS signal selects OSC: F

CLK OUT = FOSC

•

Any value between FFh down to 00h can be written by software into CKRL register

in order to divide frequency of the selected oscillator:

–

CKRL = 00h: minimum frequency

CLK CPU = FCLK PERIPH = FOSC/1020 (Standard Mode)

CLK CPU = FCLK PERIPH = FOSC/510 (X2 Mode)

–

CKRL = FFh: maximum frequency

CLK CPU = FCLK PERIPH = FOSC/2 (Standard Mode)

CLK CPU = FCLK PERIPH = FOSC (X2 Mode)

–F

CLK CPU and FCLK PERIPH

In X2 mode:

In X1 mode:

7654

3210

--------

Bit

Number

Bit

Mnemonic Description

7:0

CKRL

Clock Reload Register: Prescaler value

FCPU F

CLKPERIPH

FOSC

2255

CKRL

–

()

----------------------------------------------

FCPU F

CLKPERIPH

FOSCA

4255

CKRL

–

()

----------------------------------------------

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