ATMEGA406_0607 datasheet(39/263 Pages) ATMEL

39 / 263 page

2548E–AVR–07/06

ATmega406

System Control and Reset

9.1

Resetting the AVR

During reset, all I/O Registers are set to their initial values, and the program starts execution

from the Reset Vector. The instruction placed at the Reset Vector must be a JMP – Absolute

Jump – instruction to the reset handling routine. If the program never enables an interrupt

source, the Interrupt Vectors are not used, and regular program code can be placed at these

locations. This is also the case if the Reset Vector is in the Application section while the Interrupt

Vectors are in the Boot section or vice versa. The circuit diagram in Figure 9-1 shows the reset

logic.

The I/O ports of the AVR are immediately reset to their initial state when a reset source goes

active. This does not require any clock source to be running.

After all reset sources have gone inactive, a delay counter is invoked, stretching the internal

reset. This allows the voltage regulator to reach a stable level before normal operation starts.

The time-out period of the delay counter is defined by the user through the SUT Fuses. The dif-

ferent selections for the delay period are presented in ”Clock Sources” on page 26.

9.2

Reset Sources

The ATmega406 has several reset sources:

• Power-on Reset. If the chip is in Power-off mode, the Charger Detect module generates a reset

pulse when a charger is connected.See ”Power-on Reset and Charger Connect” on page 40

for details.

• External Reset. The MCU is reset when a low level is present on the RESET pin for longer than

the minimum pulse length. See ”External Reset” on page 41 for details.

• Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the

Watchdog is enabled. See ”Watchdog Reset” on page 42 for details.

• Brown-out Reset. The MCU is reset when VREG is below the Brown-out Reset Threshold,

BOT. See ”Brown-out Detection” on page 42 for details.

• JTAG AVR Reset. The MCU is Reset as long as there is a logic one in the Reset Register, one

of the scan chains of the JTAG system. See ”JTAG Interface and On-chip Debug System” on

page 171 for details.

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