ATMEGA406_0607 datasheet(26/263 Pages) ATMEL

26 / 263 page

2548E–AVR–07/06

ATmega406

7.1.5

Voltage ADC Clock – clk

VADC

The Voltage ADC is provided with a dedicated clock domain. This allows halting the CPU and

I/O clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC

conversion results.

7.1.6

Coulomb Counter ADC Clock - clk

CCADC

The Coulomb Counter ADC is provided with a dedicated clock domain. This allows operating the

Coulomb Counter ADC in low power modes like Power-save for continuous current

measurements.

7.1.7

Watchdog Timer and Battery Protection Clock

The Watchdog Timer and Battery Protection are provided with a dedicated clock domain. This

allows operation in all modes except Power-off. It also allows very low power operation by utiliz-

ing an Ultra Low Power RC Oscillator dedicated to this purpose.

7.2

Clock Sources

The device has the following clock sources. The clocks are input to the AVR clock generator,

and routed to the appropriate modules.

7.3

Calibrated Fast RC Oscillator

The calibrated Fast RC Oscillator by default provides a 4.0 MHz clock, which is divided down to

1.0 MHz to all modules except the TWI. The frequency is nominal value at 25

°C. This clock will

operate with no external components. During reset, hardware loads the calibration byte into the

FOSCCAL Register and thereby automatically calibrates the Fast RC Oscillator. At 25

°C, this

calibration gives a frequency of 4 MHz ± 3%. The oscillator can be calibrated to any frequency in

the range 3.7 - 4.0 MHz within ±1% accuracy, by changing the FOSCCAL register. For more

information on the pre-programmed calibration value, see the section ”Calibration Bytes” on

page 198.

The start-up times for the Fast RC Oscillator are determined by the SUT Fuses as shown in

Table 7-1 on page 26.

Note:

1. The device is shipped with this option selected.

Table 7-1.

Start-up times for the internal calibrated RC Oscillator clock selection

SUT1:0

Start-up Time from Power-down

and Power-save

Additional Delay from Reset

6 CK

14CK

6 CK

14CK + 4.1 ms

6 CK

14CK + 65 ms(1)

Reserved

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