WM9707

Production Data

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PD Rev 4.1 June 2006

16

There is no provision for pseudo-stereo effects. Mono signals will have no enhancement applied

(if the signals are in phase and of the same amplitude).

Signals from the PCM DAC channels can have stereo enhancement applied. It can also be bypassed

if desired. This control is enabled by setting the POP bit in Register 20h.

VARIABLE SAMPLE RATE SUPPORT

The DACs and ADCs on this device support all the recommended sample rates specified in the Intel

Revision 2.1 specification for audio rates. The default rate is 48ks/s. If alternative rates are selected

and variable rate audio is enabled (Register 2Ah, bit 0), the AC’97 interface continues to run at 48k

words per second, but data is transferred across the link in bursts such that the net sample rate

selected is achieved. It is up to the AC’97 Revision 2.1 compliant controller to ensure that data is

supplied to the AC link, and received from the AC link, at the appropriate rate.

The device supports on demand sampling. That is, when the DAC signal processing circuits need

another sample, a sample request is sent to the controller which must respond with a data sample in

the next frame it sends. For example, if a rate of 22.05ks/s is selected, on average the device will

request a sample from the controller every other frame, for each of the stereo DACs. Note that if an

unsupported rate is written to one of the rate registers, the rate will default to the nearest rate

supported. The Register will then respond when interrogated with the supported rate the device has

defaulted to.

The left and right channels of the ADCs and DACs always sample at the same rate.

AUDIO

SAMPLE RATE

(HZ)

CONTROL VALUE

D15-D0

(HEX)

8000

1F40

11025

2B11

16000

3E80

22050

5622

32000

7D00

44100

AC44

48000

BB80

Table 1 Variable Sample Rates Supported

SPDIF DIGITAL AUDIO DATA OUTPUT

Pin 48 may be used to output the PCM DAC playback data in SPDIF (IEC958) digital data format. In

order to enable this output, bit SPDF in Register 5Ch should be set or pin 44 pulled high.

Additionally, a bit SCMS in Register 5Ch may also be set, which removes the copyright flag in the

IEC958 data, allowing serial copy protect mechanisms to be implemented. Note that this data output

will only operate at the SYNCH rate and so only supports 48ks/s operation. The PCM DACs continue

to function normally when SPDIF output is enabled.

GAIN CONTROL REGISTER LOCATION

PGA

CONTROL REGISTER

MUTE DEFAULT

DAC

18h

Muted (bit-15)

Mixer

72h

Not-muted (bit-15)

Volume

02h

Muted (15)

Table 2 Gain Control Register Location