WM9707

Production Data

w

PD Rev 4.1 June 2006

15

DEVICE DESCRIPTION

INTRODUCTION

The WM9707 is fully compliant with Revision 2.1 of the AC’97 specification.

The WM9707 comprises a stereo 18-bit CODEC, (that is, 2 ADCs and 2 DACs) a comprehensive

analogue mixer with 4 sets of stereo inputs, phone, 2 microphone, and PC-beep inputs. Additionally,

on-chip reference generation circuits generate the necessary bias voltages for the device, and a

bidirectional serial interface allows transfer of control data and DAC and ADC words to and from the

AC’97 controller. The WM9707 supports 18-bit resolution within the DAC and ADC functions, but the

AC’97 serial interface specification allows any word length up to 20-bits to be written to, or read from,

the AC’97 CODEC. These words are MSB justified, and any LSBs not used will simply default to 0.

Normally it is anticipated that 16-bit words will be used in most PC type systems. Therefore, for the

DAC, 16-bit words will be downloaded into the CODEC from the controller, along with padding of 0s

to make the 16-bit word up to 20-bit length. In this case, the WM9707 will process the 16-bit word

along with 0 padding bits in the 2 LSB locations (to make 18-bit). At the ADC output, WM9707 will

provide an 18-bit word, again with 0s in the two LSB locations (20-bit). The AC’97 controller will then

ignore the 4 LSBs of the 20-bit word. When the WM9707 is interrogated at Register 00h, it responds

indicating it is an 18-bit device.

The WM9707 has the ADC and DAC functions implemented using oversampled, or sigma-delta

converters, and uses on-chip digital filters to convert these 1-bit signals to and from the 48ks/s 16/18-

bit PCM words that the AC’97 controller requires. The digital parts of the device are powered

separately from the analogue to optimise performance, and 3.3V digital and 5V analogue supplies

may be used on the same device to further optimise performance. Digital IOs are 5V tolerant when

the analogue supplies are 5V, so the WM9707 may be connected to a controller running on 5V

supplies, but use 3.3V for the digital section of WM9707. WM9707 is also capable of operating with a

3.3V supply only (digital and analogue).

An internally generated midrail reference is provided at pin CAP2 which is used as the chip

reference. This pin should be heavily decoupled. Refer to Figure 18 for more details.

The WM9707 is not limited to PC-only applications. The ability to power down sections of the device

selectively, and the option to choose alternative master clock, and hence sample rates, means that

many alternative applications in areas such as telecomms, may be anticipated.

Additional features added to the Intel AC’97 specification, such as the EAPD (External Amplifier

Powerdown) bit, internal connection of PC-beep to the outputs in the case where the device is reset,

are supported, along with optional features such as variable sample rate support and SPDIF output.

3D STEREO ENHANCEMENT

This device contains a stereo enhancement circuit, designed to optimise the listening experience

when the device is used in a typical PC operating environment. That is, with a pair of speakers

placed either side of the monitor with little spatial separation. This circuit creates a difference signal

by differencing left and right channel playback data, then filters this difference signal using lowpass

and highpass filters whose time constants are set using external capacitors connected to the CX3D

pins 33 and 34. Typically the values of 100nF and 47nF set highpass and lowpass poles at about

100Hz and 1kHz respectively. This frequency band corresponds to the range over which the ear is

most sensitive to directional effects.

The filtered difference signal is gain adjusted by an amount set using the 4-bit value written to

Register 22h bits 3 to 0. Value 0h is disable, value Fh is maximum effect. Typically a value of 8h is

optimum. The user interface would most typically use a slider type of control to allow the user to

adjust the level of enhancement to suit the program material. Bit D13 3D in Register 20h is the

overall 3D enable bit. The capability Register 00h reads back the value 11000 in bits D14 to D10.

This corresponds to decimal 24, which is registered with Intel as Wolfson Stereo Enhancement.

Note that the external capacitors setting the filtering poles applied to the difference signal may be

adjusted in value, or even replaced with a direct connection between the pins. If such adjustments

are made, then the amount of difference signal fed back into the main signal paths may be

significant, and can cause large signals which may limit, distort, or overdrive signal paths or

speakers. Adjust these values with care, to select the preferred acoustic effect.