 |
công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
|
công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
VSC8541XMV-05 bảng dữ liệu(PDF) 92 Page - Microchip Technology |
|
|
|||||||||||||||||||||||||||||
VSC8541XMV-05 bảng dữ liệu(HTML) 92 Page - Microchip Technology |
|
|
92 / 101 page  Pin Descriptions VMDS-10513 VSC8541-02 Datasheet Revision 4.1 83 R/GMII COL 18 I/O, PD VDDMAC GMII/MII collision output. The logic state on this pin is latched on the rising edge of NRESET to configure the device. See "Hardware Mode Strapping and PHY Addressing" for details. R/GMII CRS 19 I/O, PD VDDMAC GMII/MII carrier sense output. The logic state on this pin is latched on the rising edge of NRESET to configure the device. See "Hardware Mode Strapping and PHY Addressing" for details. R/GMII GTX_CLK 37 I, PD VDDMAC GMII/RGMII transmit clock input R/GMII MII_TXCLK 36 I/O, PD VDDMAC MII transmit clock output. The logic state on this pin is latched on the rising edge of NRESET to configure the device. See "Hardware Mode Strapping and PHY Addressing" for details. R/GMII RX_CLK 32 I/O, PD VDDMAC GMII/MII receive clock output. The logic state on this pin is latched on the rising edge of NRESET to configure the device. See "Hardware Mode Strapping and PHY Addressing" for details. R/GMII RX_DV/RX_CTL 30 I/O, PD VDDMAC GMII/MII receive data valid output/RGMII receive control output. The logic state on this pin is latched on the rising edge of NRESET to configure the device. See "Hardware Mode Strapping and PHY Addressing" for details. R/GMII RX_ER 31 I/O, PD VDDMAC GMII/MII receive data error output. The logic state on this pin is latched on the rising edge of NRESET to configure the device. See "Hardware Mode Strapping and PHY Addressing" for details. R/GMII RXD0 29 I/O, PD VDDMAC GMII/MII/RGMII data output. The logic state on this pin is latched on the rising edge of NRESET to configure the device. See "Hardware Mode Strapping and PHY Addressing" for details. R/GMII RXD1 27 I/O, PD VDDMAC GMII/MII/RGMII data output. The logic state on this pin is latched on the rising edge of NRESET to configure the device. See "Hardware Mode Strapping and PHY Addressing" for details. R/GMII RXD2 26 I/O, PD VDDMAC GMII/MII/RGMII data output. The logic state on this pin is latched on the rising edge of NRESET to configure the device. See "Hardware Mode Strapping and PHY Addressing" for details. |
|
Link URL |
| Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không? [ DONATE ] |
Alldatasheet là | Quảng cáo | Liên lạc với chúng tôi | Chính sách bảo mật | Liên kết đến bảng dữ liệu | Trao đổi link | Tìm kiếm theo nhà sản xuất All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Vietnamese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
