VSC8541XMV-05 datasheet(29/101 Pages) MICROCHIP

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Functional Descriptions

VMDS-10513 VSC8541-02 Datasheet Revision 4.1

•

Data—The 16-bits read from or written to the device are considered the data or data stream. When

data is read from a PHY, it is valid at the output from one rising edge of MDC to the next rising edge

of MDC. When data is written to the PHY, it must be valid around the rising edge of MDC.

•

Idle—The sequence is repeated.

3.10.2

SMI Interrupt

The SMI includes an interrupt signal, MDINT, for signaling the station manager when certain events occur

in the VSC8541-02 device.

When a PHY generates an interrupt, the MDINT pin is asserted by driving low if the interrupt pin enable

bit (register 25.15) is set. The MDINT pin is configured for open-drain (active-low) operation. Tie the pin

to a pull-up resistor to VDDMDIO. The following illustration shows the configuration.

Figure 16 •

MDINT Configured as an Open-Drain (Active-Low) Pin

3.11

LED Interface

The LED interface supports direct drive and basic serial LED mode configuration. The polarity of the LED

outputs is programmable and can be changed using register 17E2, bits 13:10. The default polarity is

active low.

Direct drive mode provides two LED signals, LED0 and LED1. The mode and function of each LED

signal can be configured independently.

In basic serial LED mode, all signals that can be displayed on LEDs are sent as LED_Data and

LED_CLK for external processing.

The following table shows the bit 9 settings for register 14G that are used to control the LED behavior for

all the LEDs in the VSC8541-02 device.

3.11.1

LED Modes

Each LED pin can be configured to display different status information that can be selected by setting the

LED mode in register 29. The default LED state is active low and can be changed by modifying the value

in register 17E2, bits 13:10. The blink/pulse stretch is dependent on the LED behavior setting in register

30.

Table 13 •

LED Drive State

Setting

Active

Not Active

14G.9 = 1 (default)

Ground

Tristate

14G.9 = 0 (alternate setting) Ground

VDD

MDINT

(to the Station

Manager)

Interrupt Pin Enable

(Register 25.15)

Interrupt Pin Status

(Register 26.15)

External Pull-up

Resistor at the

Station Manager

VDDMDIO

PHY_n

MDINT

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