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IMX8ULPIEC bảng dữ liệu(PDF) 74 Page - NXP Semiconductors |
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IMX8ULPIEC bảng dữ liệu(HTML) 74 Page - NXP Semiconductors |
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74 / 100 page ![]() 7 Specifications—real-time domain 7.1 Real time domain (RTD) power modes Table 54. RTD power modes Power Mode Min. Voltage at the pin (V) VDD_DIG0 Max Frequency (MHz) CM33/ Fusion DSP Biasing Setting Description Active Over Drive 1.05 216/200 AFBB enabled All logic is functional in this mode. Allows Dynamic Voltage Scaling(DVS) Normal Drive 1 127/127 AFBB enabled Under Drive 0.9 38.4/38.4 ARBB enabled Sleep 0.9 - RBB enabled (optional) Core in Wait-for- Interrupt (WFI) Core, bus, peripheral clock gating configurable by software Deep Sleep 0.65 - RBB enabled Core is in wait- for-interrupt(WFI) state Core/System clock gated Some peripheral optional functional SRAM contents retained POWER DOWN 0.65 - RBB enabled Core/System/ peripherals power gated SRAM with configurable retention Comparator, LP timers optionally functional DEEP POWER DOWN - - - RTD domain completely power gated Table continues on the next page... NXP Semiconductors Specifications—real-time domain i.MX 8ULP Applications Processor—Industrial Products, Rev. 1, 09/2023 Data Sheet: Technical Data 74 / 100 |
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