IMX8ULPIEC datasheet(35/100 Pages) NXP

35 / 100 page

Table 16. Clock frequencies (continued)

Clock name

Voltage range at the pin

1.05 V

1.0 V

0.9 V w/ARBB

WDOG

—

SAI1

—

HIFI4_CLK

475

264

—

NIC_HIFI4_CLK

238

132

—

NIC_LPAV_AXI_CLK

316.8

198

—

NIC_LPAV_AHB_CLK

158.4

—

LPAV_BUS_CLK

79.2

—

DDR_CLK

2661, 2

200

—

DDR PHY

5281

400

—

GPU3D

288

198

—

GPU2D

288

198

—

DCNano

105

—

MIPI CSI

140

—

MIPI CSI UI

—

ISI

—

MIPI CSI ESC

—

EPDC

297

198

—

WDOG5

—

LPTPM8

—

1. Supported only for LPDDR4/4x

2. The PLL4 PFD0 PLL output clock maximum frequency when VDD_DIG2 = 1.0 V nominal is 528 MHz. The PLL2_VCO

output clock maximum frequency when VDD_DIG1 = 1.0 V nominal is 725 MHz. When VDD_DIG0, VDD_DIG1 or

VDD_DIG2 is at 0.9 V nominal, the fastest selectable clock source available is the FRO192 for the corresponding domain

4.3 Power sequencing—system

4.3.1 Power-on sequencing

The power-on sequencing requirements for the device are described in this section.

VBAT Domain Power Supply

VDD_VBAT42 must be powered and stable before all other supplies begin to ramp up.

Real-Time Domain Power Supplies

The Real-Time Domain supplies must be powered and stable before RESET0_B is deasserted. The real-time domain supplies

listed below may be powered on in any order except for those indicating specific sequencing requirements.

NXP Semiconductors

System specifications

i.MX 8ULP Applications Processor—Industrial Products, Rev. 1, 09/2023

Data Sheet: Technical Data

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