ES9028Q2M datasheet(33/45 Pages) ESS

33 / 45 page

January 16, 2020

0.41

ES9028Q2M Datasheet

ESS TECHNOLOGY, INC. 109 Bonaventura Dr., San Jose, CA 95134, USA. Tel (408) 643-

8800 • WWW.ESSTECH.COM

XI / MCLK Timing

MCH

MCL

MCY

MCLK

MCH

MCL

MCY

MCLK

Parameter

Symbol

Min

Max

Unit

MCLK pulse width high

TMCH

4.5

MCLK pulse width low

TMCL

4.5

MCLK cycle time

TMCY

MCLK duty cycle

45:55

55:45

Audio Interface Timing

DCH

DCL

DCY

DATA_CLK

DATA[8:1]

Valid

Invalid

Valid

DCH

DCL

DCY

DATA_CLK

DATA[8:1]

Valid

Invalid

Valid

DATA_CLK

DATA[2:1]

Parameter

Symbol

Min

Max

Unit

DATA_CLK pulse width high

tDCH

4.5

DATA_CLK pulse width low

tDCL

4.5

DATA_CLK cycle time

tDCY

DATA_CLK duty cycle

45:55

55:45

DATA set-up time to DATA_CLK rising edge

tDS

4.1

DATA hold time to DATA_CLK rising edge

tDH

Notes:

•

Audio data on DATA[2:1] are sampled at the rising edges of DATA_CLK and must satisfy the setup and hold time

requirements relative to the rising edge of DATA_CLK

•

For DSD Phase mode, the normal data (D0, D1, D2... on p.10) must satisfy the setup and hold time requirements relative

to the rising edge of DATA_CLK. The complimentary data (D0, D1, etc.) will be ignored.

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