ES9028Q2M datasheet(26/45 Pages) ESS

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January 16, 2020

ES9028Q2M Datasheet

ESS TECHNOLOGY, INC. 109 Bonaventura Dr., San Jose, CA 95134, USA. Tel (408) 643-

8800 • WWW.ESSTECH.COM

16-bit, Read-Write Register, Default = 0x0000 (no compensation). Register #35 is MSB.

See Registers #13, #22-25, and #38 for more details.

Bits

[15:0]

Mnemonic

Thd_comp_c2_right

Default

16’d0

16-bit, Read-Write Register, Default = 0x0000 (no compensation). Register #37 is MSB.

See Registers #13, #22-25, and #38 for more details.

Bits

[15:0]

Mnemonic

Thd_comp_c3_right

Default

16’d0

8-bit, Read-Write Register, Default = 0x00

Bits

[7:1]

[0]

Mnemonic

reserved *

enable_separate_thd_comp

Default

Bit

Mnemonic

Description

[7:1]

reserved *

[0]

enable_separate_thd_comp

1'b0: (default)

•

left/right THD compensation coefficients are taken from registers #25-22

1’b1:

•

left THD compensation coefficients are taken from registers #25-22

•

right THD compensation coefficients are taken from registers #37-34

* All Reserved Bits in Register #38 must be set to the indicated logic level to ensure correct device operation.

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