January 16, 2020

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ES9028Q2M Datasheet

19

ESS TECHNOLOGY, INC. 109 Bonaventura Dr., San Jose, CA 95134, USA. Tel (408) 643-

8800 • WWW.ESSTECH.COM

Register #12: DPLL/ASRC Settings

8 bit, Read-Write Register, Default = 0x5A

Bits

[7]

[6]

[5]

[4]

[3]

[2]

[1]

[0]

Mnemonic

dpll_bw_i2s

dpll_bw_dsd

Default

0

1

0

1

1

0

1

0

Bit

Mnemonic

Description

[7:4]

dpll_bw_i2s

DPLL bandwidth setting for I2S and SPDIF modes (16 settings)

4’b0000 : OFF

4’b0001 : Lowest Bandwidth

4’b0101 : (default)

4’b1010 :

4’b1111 : Highest Bandwidth

[3:0]

dpll_bw_dsd

DPLL bandwidth setting for DSD mode (16 settings)

4’b0000 : OFF

4’b0001 : Lowest Bandwidth

4’b0101 :

4’b1010 : (default)

4’b1111 : Highest Bandwidth

The ES9028Q2M contains a Jitter Eliminator block, which employs the use of a digital phase locked loop (DPLL) to lock to

the incoming audio clock rate. When in I2S or SPDIF mode, the DPLL will lock to the frame clock (1 x fs). However, when in

DSD mode, the DPLL has no frame clock information, and must instead lock to the bit clock rate (BCK). For this reason,

there are two bandwidth settings for the DPLL.

Register #12 [7:4] (0x05 default) contains the bandwidth setting for I2S / SPDIF mode.

Register #12 [3:0] (0x0A default) contains the bandwidth setting for DSD mode.

The DPLL bandwidth sets how quickly the DPLL can adjust its internal representation of the audio clock. The higher the jitter

or frequency drift on the audio clock, the higher the DPLL bandwidth must be so that the DPLL can react.