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UPD75P3018A bảng dữ liệu(PDF) 20 Page - Renesas Technology Corp |
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UPD75P3018A bảng dữ liệu(HTML) 20 Page - Renesas Technology Corp |
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20 / 66 page ![]() µPD75P3018A 18 Data Sheet U11917EJ2V1DS Figure 6-3. Program Memory Map (Mk II mode) Caution To allow the vectored interrupt’s 14-bit start address (noted above), set the address within a 16K area (0000H to 3FFFH). Remark For instructions other than those noted above, the BR PCDE and BR PCXA instructions can be used to branch to addresses with changes in the PC’s low-order 8 bits only. MBE MBE MBE MBE MBE MBE MBE RBE RBE RBE RBE RBE RBE RBE Internal reset start address (high-order 6 bits) Internal reset start address (low-order 8 bits) INTBT/INT4 start address (high-order 6 bits) INTBT/INT4 start address (low-order 8 bits) INT0 start address (high-order 6 bits) INT0 start address (low-order 8 bits) INT1 start address (high-order 6 bits) INT1 start address (low-order 8 bits) INTCSI start address (high-order 6 bits) INTCSI start address (low-order 8 bits) INTT0 start address (high-order 6 bits) INTT0 start address (low-order 8 bits) INTT1, INTT2 start address (high-order 6 bits) INTT1, INTT2 start address (low-order 8 bits) Reference table for GETI instruction 0000H 0002H 0004H 0006H 0008H 000AH 000CH 1FFFH 2000H 2FFFH 3000H 3FFFH 4000H 4FFFH 5000H 5FFFH 6000H 6FFFH 7000H 7FFFH 0020H 007FH 0080H 07FFH 0800H 0FFFH 1000H CALLF !faddr instruction entry address BR !addr instruction branch address CALL !addr instruction branch address Branch/call address by GETI BRCB !caddr instruction branch address BRCB !caddr instruction branch address BRCB !caddr instruction branch address 76 5 0 BRCB !caddr instruction branch address BRCB !caddr instruction branch address BRCB !caddr instruction branch address BRCB !caddr instruction branch address BRCB !caddr instruction branch address Branch addresses for the following instructions • BR BCDE • BR BCXA • BRA !addr1 • CALLA !addr1 BR $addr1 instruction relative branch address (–15 to –1, +2 to +16) |
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