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UPD75P3018A bảng dữ liệu(PDF) 29 Page - Renesas Technology Corp

tên linh kiện UPD75P3018A
Giải thích chi tiết về linh kiện  MOS INTEGRATED CIRCUIT
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UPD75P3018A bảng dữ liệu(HTML) 29 Page - Renesas Technology Corp

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µPD75P3018A
27
Data Sheet U11917EJ2V1DS
Instruction
Mnemonic
Operand
No. of Machine
Operation
Addressing
Skip
Group
Bytes
Cycle
Area
Condition
Branch
BRNote 1
addr
—
—
PC14
← 0, PC13-0 ← addr
*6
Use the assembler to select the
most appropriate instruction
among the following.
• BR !addr
• BRCB !caddr
• BR $addr
addr1
—
—
PC14-0
← addr1
*11
Use the assembler to select
the most appropriate instruction
among the following.
• BRA !addr1
• BR !addr
• BRCB !caddr
• BR $addr1
!addr
3
3
PC14
← 0, PC13-0 ← addr
*6
$addr
1
2
PC14
← 0, PC13-0 ← addr
*7
$addr1
1
2
PC14-0
← addr1
PCDE
2
3
PC14
← 0, PC13-0 ← PC13-8+DE
PC14-0
← PC14-8+DE
PCXA
2
3
PC14
← 0, PC13-0 ← PC13-8+XA
PC14-0
← PC14-8+XA
BCDE
2
3
PC14
← 0, PC13-0 ← BCDENote 2
*6
PC14-0
← BCDENote 2
*11
BCXA
2
3
PC14
← 0, PC13-0 ← BCXANote 2
*6
PC14-0
← BCXANote 2
*11
BRANote 1
!addr
3
3
PC14
← 0, PC13-0 ← addr
*6
33
PC14-0
← addr1
*11
BRCBNote 1
!caddr
2
2
PC14
← 0, PC13-0 ← PC13, 12+caddr11-0
*8
PC14-0
← PC14, 13, 12+caddr11-0
Notes 1. Shaded areas indicate support for Mk II mode only. Other areas indicate support for Mk I mode only.
2. The only following bits are valid in the B register.
For Mk I mode : Low-order 2 bits
For Mk II mode : Low-order 3 bits



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