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UPD75P3018A bảng dữ liệu(PDF) 19 Page - Renesas Technology Corp |
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UPD75P3018A bảng dữ liệu(HTML) 19 Page - Renesas Technology Corp |
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19 / 66 page ![]() µPD75P3018A 17 Data Sheet U11917EJ2V1DS Figure 6-2. Program Memory Map (Mk I mode) Remark For instructions other than those noted above, the BR PCDE and BR PCXA instructions can be used to branch to addresses with changes in the PC’s low-order 8 bits only. MBE MBE MBE MBE MBE MBE MBE RBE RBE RBE RBE RBE RBE RBE Internal reset start address (high-order 6 bits) Internal reset start address (low-order 8 bits) INTBT/INT4 start address (high-order 6 bits) INTBT/INT4 start address (low-order 8 bits) INT0 start address (high-order 6 bits) INT0 start address (low-order 8 bits) INT1 start address (high-order 6 bits) INT1 start address (low-order 8 bits) INTCSI start address (high-order 6 bits) INTCSI start address (low-order 8 bits) INTT0 start address (high-order 6 bits) INTT0 start address (low-order 8 bits) INTT1, INTT2 start address (high-order 6 bits) INTT1, INTT2 start address (low-order 8 bits) Reference table for GETI instruction 0000H 0002H 0004H 0006H 0008H 000AH 000CH 007FH 0080H 07FFH 0800H 0FFFH 1000H 1FFFH 2000H 2FFFH 3000H 3FFFH CALLF !faddr instruction entry address Branch addresses for the following instructions • BR BCDE • BR BCXA • BR !addr • CALL !addr Branch/call address by GETI BR $addr instruction relative branch address (–15 to –1, +2 to +16) BRCB !caddr instruction branch address BRCB !caddr instruction branch address BRCB !caddr instruction branch address BRCB !caddr instruction branch address 76 5 0 0020H |
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