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UPD75P3018A bảng dữ liệu(PDF) 57 Page - Renesas Technology Corp |
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UPD75P3018A bảng dữ liệu(HTML) 57 Page - Renesas Technology Corp |
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57 / 66 page ![]() µPD75P3018A 55 Data Sheet U11917EJ2V1DS APPENDIX A. µPD75316B, 753017A AND 75P3018A FUNCTION LIST Parameter µPD75316B µPD753017A µPD75P3018A Program memory Mask ROM Mask ROM One-time PROM 0000H-3F7FH 0000H-5FFFH 0000H-7FFFH (16256 × 8 bits) (24576 × 8 bits) (32768 × 8 bits) Data memory 000H-3FFH (1024 × 4 bits) CPU 75X Standard 75XL CPU Instruction When main system 0.95, 1.91, or 15.3 µs• 0.95, 1.91, 3.81, or 15.3 µs (at 4.19 MHz operation) execution time clock is selected (at 4.19 MHz operation) • 0.67, 1.33, 2.67, or 10.7 µs (at 6.0 MHz operation) When subsystem 122 µs (at 32.768 kHz operation) clock is selected Pin connection 29 to 32 P40 to P43 P40/D0 to P43/D3 34 to 37 P50 to P53 P50/D4 to P53/D7 44 P12/INT2 P12/INT2/TI1/TI2 47 P21 P21/PTO1 48 P22/PCL P22/PCL/PTO2 50 to 53 P30 to P33 P30/MD0 to P33/MD3 57 IC VPP Stack SBS register None SBS.3 = 1; Mk I mode selection SBS.3 = 0; Mk II mode selection Stack area 000H-0FFH n00H-nFFH (n = 0-3) Subroutine call instruction 2-byte stack Mk I mode: 2-byte stack stack operation Mk II mode: 3-byte stack Instruction BRA !addr1 Unavailable Mk I mode: unavailable CALLA !addr1 Mk II mode: available MOVT XA, @BCDE Available MOVT XA, @BCXA BR BCDE BR BCXA CALL !addr 3 machine cycles Mk I mode: 3 machine cycles, Mk II mode: 4 machine cycles CALLF !faddr 2 machine cycles Mk I mode: 2 machine cycles, Mk II mode: 3 machine cycles Mask option Yes None Timer 3 channels: 5 channels: • Basic interval timer • Basic interval timer/watchdog timer: 1 channel : 1 channel • 8-bit timer/event counter: 3 channels • 8-bit timer/event counter (can be used as 16-bit timer/event counter, carrier generator, : 1 channel timer with gate) • Watch timer: 1 channel • Watch timer: 1 channel |
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