Memory Management Unit
6-2
Copyright © ARM Limited 1997, 1998, 2000. All rights reserved.
ARM DDI 0192A
6.1
About the MMU
The MMU performs two primary functions:
•
translates virtual addresses into physical addresses
•
controls memory access permissions.
The MMU hardware required to perform these functions consists of:
•
a TLB
•
access control logic
•
translation table walking logic.
When the MMU is turned off, as happens on reset, the virtual address is output directly
onto the physical address bus.
Note
The MMU works with virtual addresses after any relocation by the FCSE PID.
6.1.1
Memory accesses
The MMU supports memory accesses based on Sections or Pages:
Sections
Are 1MB blocks of memory.
Pages
Two different page sizes are supported:
•
Small pages consist of 4KB blocks of memory. Additional
access control mechanisms are extended to 1KB subpages.
•
Large pages consist of 64KB blocks of memory. Large
pages are supported to allow mapping of a large region of
memory while using only a single entry in the TLB.
Additional access control mechanisms are extended to
16KB subpages.
6.1.2
Domains
The MMU also supports the concept of domains. These are areas of memory that can
be defined to possess individual access rights. The domain access control register
specifies access rights for up to 16 separate domains.
6.1.3
TLB
The TLB caches 64 translated entries. During most memory accesses, the TLB provides
the translation information to the access control logic:
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