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ARM720T bảng dữ liệu(PDF) 32 Page - List of Unclassifed Manufacturers

tên linh kiện ARM720T
Giải thích chi tiết về linh kiện  General-purpose 32-bit Microprocessor with 8KB cache, enlarged Write buffer, and Memory Management Unit (MMU) combined in a single chip
PDF  242 Pages
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nhà sản xuất  ETC2 [List of Unclassifed Manufacturers]
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ARM720T bảng dữ liệu(HTML) 32 Page - List of Unclassifed Manufacturers

Back Button ARM720T Datasheet HTML 28Page - List of Unclassifed Manufacturers ARM720T Datasheet HTML 29Page - List of Unclassifed Manufacturers ARM720T Datasheet HTML 30Page - List of Unclassifed Manufacturers ARM720T Datasheet HTML 31Page - List of Unclassifed Manufacturers ARM720T Datasheet HTML 32Page - List of Unclassifed Manufacturers ARM720T Datasheet HTML 33Page - List of Unclassifed Manufacturers ARM720T Datasheet HTML 34Page - List of Unclassifed Manufacturers ARM720T Datasheet HTML 35Page - List of Unclassifed Manufacturers ARM720T Datasheet HTML 36Page - List of Unclassifed Manufacturers Next Button
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Introduction
1-16
Copyright © ARM Limited 1997, 1998, 2000. All rights reserved.
ARM DDI 0192A
The Thumb instruction set formats are shown in Figure 1-3.
Figure 1-3 Thumb instruction set formats
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Rd
Rd
Rb
Rb
Op
0 0 1
H1 H2
0 1 0 0 0 0
0 1 0 0 1
Ro
1 L B 0
Offset8
Op
Word8
Rd
Rn/
offset3
Rd
Rs
Op
0
0
0
1
1
1
Rd
Op
Rd
Rs
RdHd
Rs/Hs
0 1 0 0 0 1
0 1 0
Rd
Rb
Ro
1 H S 1
0 1 0
Offset5
B L
0 1 1
Rb
Rd
Offset5
0 L
1 0 0
Rd
Word8
1 L
1 0 0
Rd
Word8
0 SP
1 0 1
SWord7
0 0 0 S
1 1 0
1 0
Rlist
1 0 R
1 1 L
1 0
Rlist
Rb
0 0 L
1 1
Softset8
Cond
0 1
1 1
Value8
1 1 1 1
1 0 1
1
Offset11
0
1 1 0
1
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
03
04
06
02
05
07
08
09
10
11
12
13
14
15
16
17
18
19
Move shifted register
Move, compare, add, and subtract
immediate
ALU operation
High register operations and branch
exchange
PC-relative load
Load and store with relative offset
Load and store sign-extended byte and
halfword
Load and store with immediate offset
Load and store halfword
SP-relative load and store
Load address
Add offset to stack pointer
Push and pop registers
Multiple load and store
Add and subtract
Conditional branch
Software interrupt
Unconditional branch
Long branch with link
Offset
H
1 1 1
1
Offset5
Rd
Rs
Op
0
0
0
01



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