Programmer’s Model
ARM DDI 0192A
Copyright © ARM Limited 1997, 1998, 2000. All rights reserved.
2-13
2.7
The program status registers
The ARM720T contains a CPSR, and five SPSRs for use by exception handlers. These
registers:
•
hold information about the most recently performed ALU operation
•
control the enabling and disabling of interrupts
•
set the processor operating mode.
The arrangement of bits is shown in Figure 2-6.
Figure 2-6 Program status register format
2.7.1
The condition code flags
The N, Z, C, and V bits are the condition code flags. These can be changed as a result
of arithmetic and logical operations, and tested to determine whether an instruction
executes.
In ARM state, all instructions can be executed conditionally. In Thumb state, only the
Branch instruction is capable of conditional execution. See the ARM Architecture
Reference Manual for details.
2.7.2
The control bits
The bottom eight bits of a PSR (incorporating I, F, T, and M[4:0]) are known
collectively as the control bits. These change when an exception arises. If the processor
is operating in a privileged mode, they can also be manipulated by software.
I and F bits
These are the interrupt disable bits. When set, these disable the
IRQ and FIQ interrupts respectively.
31 30 29 28 27 26 25 24 23
8 7 6
4 3 2 1 0
Reserved
Condition
code flags
Control bits
Mode bits
State bit
FIQ disable
IRQ disable
Overflow
Carry or borrow or extend
Zero
Negative or less than
5
N Z C V ·
·
·
·
·
·
I F
M4 M3 M2 M1 M0
T
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