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Configuration
3-4
Copyright © ARM Limited 1997, 1998, 2000. All rights reserved.
ARM DDI 0192A
3.3
Registers
ARM720T contains registers that control the cache and MMU operation. These
registers are accessed using CPRT instructions to CP15 with the processor in a
privileged mode.
Only some of registers R0 to R15 are valid. An access to an invalid register causes
neither the access nor an undefined instruction trap, and therefore must never be carried
out.
3.3.1
Register 0, ID register
Reading from CP15 register 0 returns the value:
0x41807203
Note
The final nibble represents the core revision.
Table 3-1 Cache and MMU control register
Register
Register reads
Register writes
0
ID register
Reserved
1
Control
Control
2
Translation table base
Translation table base
3
Domain access control
Domain access control
4
Reserved
Reserved
5
Fault status
Fault status
6
Fault address
Fault address
7
Reserved
Cache operations
8
Reserved
TLB operations
9 – 12
Reserved
Reserved
13
Process identifier
Process identifier
14 – 15
Reserved
Reserved
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