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ARM720T bảng dữ liệu(PDF) 80 Page - List of Unclassifed Manufacturers

tên linh kiện ARM720T
Giải thích chi tiết về linh kiện  General-purpose 32-bit Microprocessor with 8KB cache, enlarged Write buffer, and Memory Management Unit (MMU) combined in a single chip
PDF  242 Pages
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nhà sản xuất  ETC2 [List of Unclassifed Manufacturers]
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ARM720T bảng dữ liệu(HTML) 80 Page - List of Unclassifed Manufacturers

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Write Buffer
5-2
Copyright © ARM Limited 1997, 1998, 2000. All rights reserved.
ARM DDI 0192A
5.1
About the write buffer
The ARM720T write buffer is provided to improve system performance. It can buffer
up to eight words of data, and four independent addresses. It can be enabled or disabled
using the W bit, bit 3, in the ARM720T control register. The buffer is disabled and
flushed on reset.
The operation of the write buffer is further controlled by the Bufferable (B) bit, which
is stored in the MMU page tables. For this reason, the MMU must be enabled before
using the write buffer. The two functions can, however, be enabled simultaneously,
with a single write to the control register.
For a write to use the write buffer, both the W bit in the control register and the B bit in
the corresponding page table must be set.
Note
It is not possible to abort buffered writes externally. The BERROR pin is ignored.
Areas of memory that can generate aborts must be marked as unbufferable in the MMU
page tables.
5.1.1
Bufferable bit
This bit controls whether a write operation uses or does not use the write buffer.
Typically, main memory is bufferable and I/O space unbufferable. The B bit can be
configured for both pages and sections.



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